ADP5076ACBZ-R7 datasheet(13/23 Pages) AD

13 / 23 page

Data Sheet

ADP5076

Rev. A | Page 13 of 23

THEORY OF OPERATION

ERROR

AMP

–

BOOST PWM

CONTROL

SW1

VPOS

FB1

COMP1

VIN

CIN

CURRENT

SENSE

SYNC

PGND

SW2

FB2

INVERTER

PWM CONTROL

PVIN

–

ERROR

AMP

EN1

EN2

AVIN

COMP2

SEQ

SLEW

AGND

CURRENT SENSE

START-UP

TIMERS

PLL

REFERENCES

4µA

REF1

REF2

REF1

REF2

SEQUENCE

CONTROL

OSCILLATOR

SLEW

1.5MΩ

BOOST_ENABLE

INVERTER_ENABLE

COUT1

RFT1

RFB1

RFT2

RFB2

COUT2

VNEG

RC1

CC1

RC2

CC2

RSS (OPTIONAL)

THERMAL

SHUTDOWN

UVLO

VREF

OVP

FB1

FB2

REFERENCE

GENERATOR

REF_1V6

CVREF

SLEW

TRI-STATE

BUFFER

1.5MΩ

Figure 39. Typical Application Circuit

PULSE WIDTH MODULATION (PWM) MODE

In PWM mode, the boost and inverting regulators in the

ADP5076 operate at a fixed frequency set by an internal

oscillator. At the start of each oscillator cycle, the MOSFET

switch turns on, applying a positive voltage across the inductor.

The inductor current increases until the current sense signal

crosses the peak inductor current threshold that turns off the

MOSFET switch. This threshold is set by the error amplifier

output. During the MOSFET off time, the inductor current

declines through the external diode until the next oscillator

clock pulse starts a new cycle. The ADP5076 regulates the output

voltage by adjusting the peak inductor current threshold.

PULSE SKIP MODULATION MODE

In pulse skip modulation operation during light load, the

regulators can skip pulses to maintain output voltage regulation.

Skipping pulses increases the device efficiency.

UVLO

The undervoltage lockout circuitry monitors the AVIN pin

voltage level. If the input voltage drops below the VUVLO_FALLING

threshold, both regulators turn off. After the AVIN pin voltage

rises above the VUVLO_RISING threshold, the soft start period initiates,

and the regulators are enabled.

OSCILLATOR AND SYNCHRONIZATION

The ADP5076 initiates the drive of the boost regulator SW1 pin

and the inverting regulator SW2 pin 180° out of phase to reduce

peak current consumption and noise.

A phase-locked loop (PLL)-based oscillator generates the

internal clock and offers a choice of two internally generated

frequency options or external clock synchronization. The

switching frequency is configured using the SYNC pin options

shown in Table 6.

For external synchronization, connect the SYNC pin to a

suitable clock source. The PLL locks to an input clock within

the range specified by fSYNC.

Table 6. SYNC Pin Options

SYNC Pin

Switching Frequency

High

2.4 MHz

Low

1.2 MHz

External Clock

1 × clock frequency

INTERNAL REGULATOR

The VREF regulator provides a reference voltage for the inverting

regulator feedback network to ensure a positive feedback voltage on

the FB2 pin.

A current-limit circuit is included for the VREF regulator to protect

the circuit from accidental loading.

ADP5076ACBZ-R7 Datasheet(PDF) 13 Page - Analog Devices

ADP5076ACBZ-R7 Datasheet(HTML) 13 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Datasheet Download

Link URL