Note:

Use pin 6 for hard processor reset under JTAG mode.

Note:

The following note below only applies to Intel Arria 10 and earlier SoC devices.

PROC_RST is not used for Intel Stratix 10 SoC devices.

HPS_nRST

directly. You should instead connect this pin to a secondary device such as

the MAX V CPLD, and use the device to manage the reset network for HPS.

2.5. Circuit Board Header Connection

The 10-pin male header, which connects to the download cable's 10-pin female plug,

has two rows of five pins. The pins are connected to the device’s programming or

configuration pins.

Caution:

If the header connection on the circuit board is a male receptacle, it must have a key

notch. Without a key notch, the 10-pin female plug will not connect. The following

figure shows a typical 10-pin male header with a key notch.

Figure 5.

10-Pin Male Header Dimensions - Inches and Millimeters

0.025 (0.635) Sq.

0.235 (5.969)

0.100

Side View

0.100(2.540)

Top View

A key notch is required.

Although a 10-pin surface mount header can be used for the cable, Intel recommends

using a through-hole connector. Through-hole connectors hold up better under the

repeated insertion and removal.

2.6. Operating Conditions

The following tables summarize the maximum ratings, recommended operating

conditions, and DC operating conditions for the download cable.

Table 4.

Intel FPGA Download Cable II Absolute Maximum Ratings

Symbol

Parameter

Conditions

Min

Max

Unit

Target supply voltage

With respect to ground

–0.5

6.5

V

USB supply voltage

With respect to ground

–0.5

6.0

V

continued...

2. Intel FPGA Download Cable II Specifications

UG-01150 | 2018.04.19

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Intel FPGA Download Cable II User Guide

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