Symbol

Parameter

Min

Max

Unit

tJPSU_TDI

JTAG port setup time

—

24.42

ns

tJPSU_TMS

JTAG port setup time

—

26.43

ns

tJPH

JTAG port hold time

—

17.25

ns

The simulated timing is based on a slow timing model, which is a worst-case scenario

environment.

For device-specific JTAG timing information, refer to the related device data sheet.

Figure 7.

Intel FPGA Download Cable II Timing Constraints

MAX

Device

Target Board

FPGA

11.575 ns

11.627 ns

JTAG Cable

JTAG

Header

Your Own

Measurement

Set Input

Delay

Board Traces

Launch/Latch

Registers

Launch/Latch

Registers

Intel FPGA Download

Cable II

If you cannot meet 24 MHz, you must decrease the frequencies to 16-6 MHz. Below is

some example code to set the TCK maximum frequency to 6 MHz:

jtagconfig --setparam 1 JtagClock 6M

Related Information

•

Changing the TCK Frequency on page 14

•

Documentation: Data Sheets

2.8. Changing the TCK Frequency

cable:

\<Intel Quartus Prime version>\quartus\bin64

).

2. Type the following command to change the TCK frequency:

jtagconfig --setparam <cable number> JtagClock <frequency><unit prefix>

Where:

2. Intel FPGA Download Cable II Specifications

UG-01150 | 2018.04.19

Intel FPGA Download Cable II User Guide

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