NXP Semiconductors

WLAN8101C

5 GHz Wi-Fi 6 Front-End Module

9 Functional description

9.1 Parallel interface control states per MIMO channel

Control pin SEL3_x, LNAEN_x, and PAEN_x contain internal pull-down resistors. The parallel interface table applies to both

_0 and _1 control pins.[1]

SEL3_x LNAEN_x PAEN_x Signal

path

Operating

mode

Mode description

LNA bias PA bias

0

0

0

-

-

high isolation (default)

off

off

0

0

1

TX to ANT TX_gain1a

high gain, high linearity, 11ax

compliant

off

on

1

0

1

TX to ANT TX_gain2a

high gain, high linearity, 3 dB back off,

11ax compliant

off

on

1

1

1

TX to ANT TX_gain3

low gain, low power, 11ax compliant

off

on

1

1

0

-

-

reserved

-

-

1

0

0

-

-

reserved

-

-

0

1

0

ANT to RX RX_gain

normal gain

on

off

0

1

1

ANT to RX RX_bypass

bypass

off

off

Table 5. Parallel interface control states per MIMO channel

[1]

WLAN8101C

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© NXP B.V. 2021. All rights reserved.

Product data sheet

Rev. 3 — 11 August 2020

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