PI3USB9281 datasheet(4/13 Pages) DIODES

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2014-04-0004

PT0502-1

04/28/14

PI3USB9281

USB 2.0 Port Protection with Charger Detection

Switch AC Electrical Characteristics

Min and Max apply for TA between -40°C to 85°C and TJ up to +125°C (unless otherwise noted). Typical values are

referenced to TA=+25°C, VBAT=3.8V.

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Units

BWUSB

-3dB Bandwidth of USB channel

1300

MHz

OIRR

OFF-Isolation

USB Mode

f=1MHz, RS=50Ω, CL=0

-70

XTALK

Active Channel

Crosstalk D+ to D-

USB Mode

f=1MHz, RS=50Ω, CL=0

-70

f=240MHz, RS=50Ω, CL=0

-30

tSK(P)

Skew of Opposite Transitions of the Same

Output (USB Mode)

tr=tf=750ps (10-90%) at

240MHz, CL=0pF, RL=50Ω

tI2CRST

Time When I

2C_SDA and I2C_SCL Both

LOW to Cause a Reset

tINTMASK

Time after INT Mask Cleared to “0” until

INTB Goes LOW to Signal the Interrupt

after Interruptible Event while INT Mask

Bit Set to “1”

tSDPDET

Time from VBUSIN Valid to VBUSOUT Valid

with

Charger

FET

Closed

and

USB

Switches

Closed

for

USB

Standard

Downstream Port

See Figure 6

200

tCHGOUT

Time from VBUSIN Valid to VBUSOUT Valid

with

Charger

FET

Closed

for

USB

Charging Ports(CDP and DCP)

See Figure 4 and Figure 5

200

tCARKIT

Time from VBUSIN Valid to Car Kit Type 1

or Type 2 Charger Detected

See Figure 8

130

tIDDET

Time from ID Not Floating to INTB LOW

to Signal Accessory Attached that is ID

Resistance-Based Only (VBUSIN Not Valid)

See Figure 9

100

2C Controller DC Electrical Characteristics

Symbol

Parameter

Fast Mode (400kHz)

Units

Min.

Max.

VIL

Low-Level Input Voltage

-0.5

0.3VDDIO

VIH

High-Level Input Voltage

0.7VDDIO

VHYS

Hysteresis of Schmitt Trigger Inputs

VDDIO>2V

0.05VDDIO

VDDIO<2V

0.1VDDIO

VOL1

Low-Level Output Voltage at 3mA Sink Current (Open-

Drain)

VDDIO>2V

0.4

VDDIO<2V

0.2VDDIO

II2C

Input Current of I

2C SDA and SCL Pins, Input Voltage 0.26V to2.34V

-10

µA

Capacitance for Each I/O Pin

2C AC Electrical Characteristics

Symbol

Parameter

Fast Mode (400kHz)

Units

Min.

Max.

fSCL

SCL Clock Frequency

400

kHz

tHDSTA

Hold Time (Repeated) START Condition

0.6

µs

tLOW

LOW Period of SCL Clock

1.3

µs

tHIGH

HIGH Period of SCL Clock

0.6

µs

tSETSTA

Set-up Time for Repeated START Condition

0.6

µs

tHDDAT

Data Hold Time

0.9

µs

tSETDAT

Data Set-up Time

(1)

100

Rsie Time of SDA and SCL Signals

(2)

20+0.1Cb

300

Fall Time of SDA and SCL Signals

(2)

20+0.1Cb

300

tSETSTO

Set-up Time for STOP Condition

0.6

µs

tBUF

Bus-Free Time between STOP and START Conditions

1.3

µs

tSP

Pulse Width of Spikes that Must Be Suppressed by the Input Filter

Notes:

1. A fast-mode I

2C-bus device can be used in a standard-mode I2C-bus system, but the requirement t

SETDAT ≥ 250ns must be met.

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