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STLC4420A Datasheet(PDF) 22 Page - STMicroelectronics |
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STLC4420A Datasheet(HTML) 22 Page - STMicroelectronics |
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22 / 40 page  Serial host interface STLC4420A 22/40 4.2 SPI mode selection As shown in Table 4, the 12 modes of operation are controlled by 4 variables in the device status/control register. When Invert Clock = 0, SPI_CLK receive edge is the rising edge and SPI_CLK transmit edge is the falling edge. The SPI_CLK polarity can be reversed by a host write to device status/control register to change the Invert Clock = 1. In this case, the SPI_CLK transmit edge becomes the rising edge and SPI_CLK receive edge becomes the falling edge. Table 4. Serial host modes of operation Invert Clock Phase Shift 3-Wire-Mode 3-Wire-Adr DataWait Name 0 0 0 X 4-Wire 1 0 0 X 4-WireInv 0 1 0 X 4WShft 1 1 0 X 4-WireInvShft 0 0 1 0 3-Wire 1 0 1 0 3-WireInv 0 1 1 0 3-WireShft 1 1 1 0 3-WireInvShft 0 0 1 1 3-WireWait1 1 0 1 1 3-WireInvWait1 0 1 1 1 3-WireShftWait1 1 1 1 1 3-WireInvShftWait1 Figure 6. Single Word Read 4-WireInvMode Figure 7. Single Word Read 4-WireShftMode |
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