STLC4420A datasheet(35/40 Pages) STMICROELECTRONICS

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STLC4420A

Registers description

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5.9

DMA data register

The data register allows the Host to read data directly from the RAM, or to write data directly

into the RAM. The Read address is post incremented by 2 after each read.

The read length is decremented by 2 after each read.

Data is prefetched into the DMA data register when the DMA Read Address is written (if the

DMA Write Enable bit is set). The Write address is post incremented by 2 after each write.

The Write Length is decremented by 2 after each write.

It is possible to intermix Reads and Writes to the DMA Data register if the both DMA Read

and Write channels are enabled.

The format of the register is defined in Table 15.

5.10

DMA write control register

The DMA write control register allows the ARM or the Host to enable the DMA write

channel. Both ARM and Host are also able to control when 32-bit APB access are utilized.

Only the ARM can modify the HostAllowed bit. When the HostAllowed bit is de-asserted the

Host is not allowed to write the DMA Write Control, Length or Base registers.

Only bits 15:0 are accessible by the Host.

The format of the register is defined in Table 15.

Table 14.

DMA write control register

Bit number

Name

Description

15:0

Data

DMA Data Register

Table 15.

DMA write control register

Bit number

Name

Description

31:8

Reserved

HostAllowed

When bit is set, the Host is allowed to write to DMA write

control, length and base registers. HostAllowed bit is only

writable by the ARM. HostAllowed default value is '1'.

'0' = Host not Allowed to write Control, Length and Base

registers.

'1' = Host IS Allowed to write Control, Length and Base

registers.

6:4

Reserved

ApbAccess

Bit must be asserted when DMA is used to write APB

registers.

'0' = Access is not to APB register

'1' = Access is to APB register

2:1

Reserved

Enable

Specifies the access direction

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