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LCK4972 Datasheet(PDF) 1 Page - Agere Systems |
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LCK4972 Datasheet(HTML) 1 Page - Agere Systems |
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1 / 20 page  Advance Data Sheet March 26, 2004 LCK4972 Low-Voltage PLL Clock Driver 1 Features s Fully integrated PLL s Output frequency up to 240 MHz s 150 ps typical cycle-to-cycle jitter s Output skews of less than 250 ps s Single 3.3 V/2.5 V ±5% supply s 52-pin TQFPT s Compatible with PowerPC ® and Pentium ® microproces- sors s Pin compatible with 972 type devices 2 Description Agere Systems’ LCK4972 is a 3.3 V/2.5 V, PLL-based clock driver designed for high-performance RISC or CISC proces- sor-based systems. The LCK4972 has output frequencies of up to 240 MHz and skews of less than 250 ps, making it ideal for synchronous systems. The LCK4972 contains 12 low-skew outputs and a feedback/sync output for flexibil- ity and simple implementation. There is a robust level of frequency programmability between the 12 low-skew outputs in addition to the input/ output relationships. This allows for very flexible programming of the input reference versus the output frequency. The LCK4972 contains a flexible output enable and disable scheme. This helps execute system debug as well as offer multiple powerdown schemes, which meet green-class machine requirements. The LCK4972 features a power-on reset function, which automatically resets the device on powerup, providing automatic synchronization between QFB and other outputs. The LCK4972 is 3.3 V/2.5 V compatible and requires no external loop filters. It has the capability of driving 50 Ω transmission lines. Series terminated lines have the ability of driving two 50 Ω lines in parallel, effectively doubling the fanout. |
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