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LCK4972 Datasheet(PDF) 3 Page - Agere Systems |
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LCK4972 Datasheet(HTML) 3 Page - Agere Systems |
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3 / 20 page  Advance Data Sheet March 26, 2004 LCK4972 Low-Voltage PLL Clock Driver Agere Systems Inc. 3 2332 (F) Figure 2-1. Logic Diagram xtal1 xtal2 VCO_Sel PLL_EN REF_SEL TCLK0 TCLK1 TCLK_Sel Ext_FB 0 1 PHASE DETECTOR LPF VCO 0 1 DQ DQ DQ DQ DQ DQ SYNC Frz SYNC Frz SYNC Frz SYNC Frz SYNC Frz Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qc0 Qc1 Qc2 Qc3 QFB QFB QSync 0 1 ÷2 12 2 2 2 2 RESET POWER-ON ÷4, ÷6, ÷8, ÷12 ÷4, ÷6, ÷8, ÷10 ÷2, ÷4, ÷6, ÷8 ÷4, ÷6, ÷8, ÷10 SYNC PULSE DATA GENERATOR OUTPUT DISABLE CIRCUITRY fselFB2 MR/OE fsela0:1 fselb0:1 fselc0:1 fselFB0:1 Frz_Clk Frz_Data Inv_Clk |
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