LCK4972 datasheet(13/20 Pages) AGERE

13 / 20 page

Advance Data Sheet

March 26, 2004

LCK4972 Low-Voltage PLL Clock Driver

Agere Systems Inc.

4.7 Power Supply Filtering

The LCK4972 is a mixed-signal product which is susceptible to random noise, especially when this noise is on the power

supply pins. To isolate the output buffer switching from the internal phase-locked loop, the LCK4972 provides separate pow-

er supplies for the internal PLL (VDDA) and for the output buffers (VDDO). In a digital system environment, besides this iso-

lation technique, it is highly recommended that both VDDA and VDD power supplies be filtered to reduce the random noise

as much as possible.

Figure 4-8 illustrates a typical power supply filter scheme. Due to its susceptibility to noise with spectral content in this range,

a filter for the LCK4972 should be designed to target noise in the 100 kHz to 10 MHz range. The RC filter in Figure 4-8 will

provide a broadband filter with approximately 100:1 attenuation for noise with spectral content above 20 kHz. More elaborate

power supply schemes may be used to achieve increased power supply noise filtering.

2344 (F)

Figure 4-8. Power Supply Filter

0.01

µF

RS = 5

Ω—10 Ω

VDD

VDDA

LCK4972

0.01

µF

3.3 V

LCK4972 Datasheet(PDF) 13 Page - Agere Systems