L9374LF datasheet(27/80 Pages) STMICROELECTRONICS

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L9374LF

Circuit description

4.2.2

Internal oscillator

The 2MHz internal oscillator (fosc, Table 26.) provides a comparison signal used to validate

the incoming CLKIN signal. If the CLKIN signal is determined to be out of range then the

internal oscillator is used to provide clock signals internal to the L9374LF. The internal

oscillator does not have the accuracy of a proper CLKIN signal. Therefore the diagnostic

filter times will reflect the accuracy of this clock for that case.

4.2.3

CLKIN signal monitoring

The CLKIN signal is an external 250 kHz or 1MHz signal from the μC to the L9374LF. This

signal is monitored to be within a specified range (fCLKIN_L <fCLKIN<fCLKIN_H,Table 17.). If the

value is out of range, then the CLKIN_F (CLKIN failure) bit is set to ‘1’. If a CLKIN failure

(fCLK out of range) is detected, the outputs are disabled and the internal 2MHz oscillator is

used as the clock for the internal logic.

4.3

Synchronization controller

Due to the natural SPI communication task time jitter, proper actuation of the outputs

requires some level of synchronization. The Synchronization Controller provides

synchronized output actuation eliminating SPI task time jitter issues.

This function forces the outputs to change their commanded state at a specified point in time

outside the SPI communication window. This also ensures a more stable SPI

communication by minimizing ground fluctuation due to output switching during periods of

SPI communications. This delay between the SPI commands and the output actuation is

programmed by setting the RESET_VALUE and SYNC_VALUE parameters located in

4.3.1

Output synchronization

The RESET_VALUE time value is determined by using the typical time between SPI cycles.

When programmed properly, the SPI communications occur at or around the

RESET_VALUE timing. The Sync Tolerance Window (STW) is an interval of time between

RESET_VALUE times where accessing the Sync Section 5.1.1: Sync + Sync-trigger register

(address 0) during this interval generates a sync failure (SYNC_F). This window is defined

by the parameters STW_V_MIN and STW_V_MAX.

The SYNC_VALUE is a programmed delay after the RESET_VALUE when the output

transitions occur. This delay is typically set as half of the RESET_VALUE. This sets the

output transitions furthest from each SPI cycle and during the STW.

Table 30. Clock validation

CLKIN

CLKIN_S 250 kHz / 1 MHz

fCLK

CLKIN_F

250 kHz

2 MHz

0 (no failure)

1 MHz

2 MHz

0 (no failure)

250 kHz

1 MHz

1 (failure)

1 MHz

250 kHz

8 MHz

1 (failure)

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