L9374LF datasheet(29/80 Pages) STMICROELECTRONICS

29 / 80 page

DocID025414 Rev 1

29/80

L9374LF

Circuit description

Normal sequence

When stepping through a normal sequence of events the following occurs:



At a SYNC_TRIG (SYNC_TRIG=’1’) command the synchronization counter, STW and

SYNC_SIG flags are reset (STW=’0’, SYNC_SIG=’0’)



The counter counts up at a rate defined by f_A = 4 kHz.



When the counter value reaches STW_V_MIN the STW flag is set (STW=’1’)



When the counter value reaches SYNC_VALUE the SYNC_TRIG flag is set

(SYNC_TRIG=’1’) which activates the most recent output commands.



When the counter value reaches the STW_V_MAX value the STW flag is reset

(STW=’0’)



When the counter value is equal to the RESET_VALUE the counter is reset and the

output signal sync_signal is reset (SYNC_SIG=’0’)

Disallowed programming states

Erroneous programming results in the STW flag being set ‘1’



If the STW_V_MIN value is higher than or equal to STW_V_MAX value the STW flag is

set (STW = 1)



If the STW_V_MAX value is higher or equal to the RESET_VALUE value the STW flag

is set (STW = 1)

Synchronization failure

Sync failure detects a timing error in the output command synchronization. The master

C

programs a timing window (STW) where accessing to the Status Register address 0 is not

allowed.If there is an access to the Status Register address 0 when the STW flag is set then

a sync-failure is generated (SYNC_F = 1). Also, a SYNC_F will be detected if there is no

SPI traffic at all between two SYNC_SIG events. This status will be read out on the

subsequent SPI transfer.

Without a SYNC_SIG or at sync-failure there is no effect for the actuation and setpoints

Synchronization controller programming

It is necessary to write into two registers (Command Register addresses 0 and 1, sections

5.1.1 and 5.1.2) to program the Synchronization Controller. The SYNC_VALUE, the

RESET_VALUE and the SYNC_TRIG values are programmed through address 0. The

SYNC_TRIG is written to once to initialize the counter. Once initialized the SYNC_TRIG bit

is reset by the controller. Subsequent SPI transfers the SYNC_TRIG bit should not be set to

avoid re-initializing the sync counter. There is no influence on the sync counter if the

SYNC_TRIG is not set. Occasionally, the sync counter may need re-initializing depending

on the timing between the RESET_VALUE and the

C loop time. The RESET_VALUE is

incremented by 1ms intervals. The SYNC_VALUE is incremented by 250

s intervals.

The STW_V_MIN and STW_V_MAX values are programmed via register 1 (Section 5.1.2).

Their interval length is dependant on the RESET_VALUE MSB (address ‘0’, bit D9)

Table 31. Sync. tolerance window interval length

RESET_VALUE (add.0, bit D9)

RESET_VALUE Duration

Sync tolerance window interval

<8ms

250 μs/bit

>8ms

500 μs/bit

L9374LF Datasheet(PDF) 29 Page - STMicroelectronics

L9374LF Datasheet(HTML) 29 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

Datasheet Download

Link URL