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STPM32 Datasheet(PDF) 7 Page - STMicroelectronics

Part # STPM32
Description  ASSP for metering applications with up to four independent 24-bit 2nd order sigma-delta ADCs, 4 MHz OSF and 2 embedded PGLNA
PDF  121 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STPM32 Datasheet(HTML) 7 Page - STMicroelectronics

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DS10272 Rev 8
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STPM32, STPM33, STPM34
List of figures
121
List of figures
Figure 1.
STPM34 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2.
STPM33 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3.
STPM32 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4.
STPM34 pinout (top view), QFN32L 5x5x1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5.
STPM33 pinout (top view), QFN32L 5x5x1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6.
STPM32 pinout (top view), QFN24L 4x4x1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7.
SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 8.
SPI enable and disable timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 9.
UART enable and disable timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10.
Output load circuit for enable and disable times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 11.
STPM34 application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12.
Active energy error vs. current gain=2x integrator off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 13.
Active energy error vs. current gain=16x integrator off. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14.
Active energy error vs. frequency gain=2x integrator off . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15.
Active energy error vs. frequency gain=16x integrator off . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 16.
Reactive energy error vs. current gain=2x integrator off. . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 17.
Reactive energy error vs. current gain=16x integrator off. . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 18.
Reactive energy error vs. frequency gain=2x integrator off . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 19.
Reactive energy error vs. frequency gain=16x integrator off . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 20.
Active energy error vs. current gain=16x integrator on. . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 21.
Reactive energy error vs. current gain=16x integrator on. . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 22.
Power management internal connection scheme and polarization. . . . . . . . . . . . . . . . . . . 32
Figure 23.
Temperature compensation typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 24.
Analog front end internal scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 25.
Block diagram of the modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 26.
Different oscillator circuits (a): with quartz; (b): with external source . . . . . . . . . . . . . . . . . 35
Figure 27.
Clock feed for multiple devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 28.
Power-on-reset sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 29.
Global startup reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 30.
DSP block functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 31.
Filter block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 32.
DSP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 33.
Active power and energy calculation block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 34.
Fundamental active power and energy calculation block diagram . . . . . . . . . . . . . . . . . . . 44
Figure 35.
Reactive power and energy calculation block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 36.
Apparent power and energy calculation block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 37.
Power sign status bit delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 38.
RMS block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 39.
Zero-crossing generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 40.
Zero-crossing signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 41.
Phase meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 42.
Sag and swell detection blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 43.
Sag detection process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 44.
Swell detection process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 45.
AH accumulation block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 46.
AH accumulation thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 47.
Startup interface selection timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 48.
Single communication time frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68



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