STPM32 datasheet(31/121 Pages) STMICROELECTRONICS

31 / 121 page

DS10272 Rev 8

31/121

STPM32, STPM33, STPM34

Theory of operation

121

8.2

Functional description of the analog part

The analog part of the STPM3x consists of the following sections:



Power management section:

–

Reference voltage generators with programmable independent temperature

compensation

–

+3 V low drop supply voltage regulator

–

+1.2 V low drop supply voltage regulator



Analog front end section:

–

Preamplifiers in the two current channels

–2nd order sigma-delta modulators



Clock generator



Power-on-reset (POR)

8.2.1

Power management section

Supply pins for the analog part are: VCC, VDDA, VDDD and GND.

GND pins represent the reference point.

VCC pin is the power supply input namely +3.3 V to GND_REG, it has to be connected to

GND_REG via a 1 μF capacitor.

VDDA and VDDD are analog output pins of internal +3.0 V and +1.2 V low drop voltage

regulators.

At least 1 μF capacitor should be connected between VDDA and GNDA. At least 1 μF

(better 4.7 μF) capacitor should be connected between VDDD and GNDD. The input of the

mentioned regulators is VCC.

There are two voltage references embedded in the STPM33 and STPM34, while the

STPM32 embeds a single reference.

It is possible to switch off each reference voltage and each voltage or current channel

independently for power saving purpose.

EN_REF1 and EN_REF2 bits in DSP_CR1 and DSP_CR2 switch on/off the voltage

reference.

To disable a single voltage or current channel, enV1, enC1 bits for primary channel and

enV2, enC2 for secondary channel should be cleared in DFE_CR1 and DFE_CR2

respectively. Switching off some channels allows an operating current reduction as reported

in Table 5 on page 17.

As described in Figure 22, two EN_REF1 and EN_REF2 bits enable the voltage references;

if a unique voltage reference is used, one of these two bits must be disabled and VREF1

and VREF2 pins must be shorted; if an external reference is used both bits must be disabled

and the external reference must be connected to VREF1, VREF2 pins. VREF1 and VREF2

outputs should be connected to GNDREF via a 100 nF capacitor independently.

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