HC705V8GRSSLASHD datasheet(26/172 Pages) NXP

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SECTION 2: MEMORY MAP

Page 15

MC68HC705V8 Specification Rev. 2.1

SECTION 2

MEMORY MAP

2.1

SINGLE-CHIP MODE MEMORY MAP

When the MC68HC705V8 is in the Single-Chip Mode the I/O and peripherals, user RAM,

EEPROM and user EPROM are all active as shown in Figure 2-1.

Figure 2-1:

MC68HC705V8 Single-Chip Mode Memory Map

2.2

I/O AND CONTROL REGISTERS

The I/O and Control Registers reside in locations $0000-$003F. The overall organization of

these registers is shown in Figure 2-2. The bit assignments for each register are shown in

Figure 2-3, Figure 2-4, Figure 2-5, and Figure 2-6. Reading from unimplemented bits will

return unknown states, and writing to unimplemented bits will be ignored.

0704

0703

User Vectors EPROM

16 Bytes

Bootload/ Factory test

code

ROM 1008 Bytes

16383

16368

16367

Stack

(64 Bytes)

User RAM

320 Bytes

Reset Vector (Low Byte)

Reset Vector (High Byte)

SWI Vector (Low Byte)

SWI Vector (High Byte)

IRQ Vector (Low Byte)

IRQ Vector (High Byte)

16-Bit Timer Vector (Low Byte)

16-Bit Timer Vector (High Byte)

$3FF7

$3FF8

$3FF9

$3FFA

$3FFB

$3FFC

$3FFD

$3FFE

$3FFF

MDLC (Low Byte)

$003F

$0000

$0100

$00FF

0255

0256

I/O

64 Bytes

0064

0063

0000

$3FFF

$3FF0

$3FEF

$0040

$003F

$0000

User EPROM

12032 Bytes

I/O

Registers

64 Bytes

(See Figure 2-2)

$3FF6

MDLC (High Byte)

$3FF3

8-Bit Timer (Low Byte)

$3FF4

SPI (High Byte)

$3FF5

SPI (Low Byte)

$3FF2

8-Bit Timer (High Byte)

$3FF1

unused

$3FF0

COP Watchdog Timer

15360

15359

$3C00

$3BFF

$0D00

$0CFF

User EEPROM

128 Bytes

3328

3327

Unused

2624 Bytes

$02C0

$02BF

$0240

$023F

0575

0576

Mask Option Register

User RAM

(128 Bytes)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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