HC705V8GRSSLASHD datasheet(76/172 Pages) NXP

76 / 172 page

SECTION 8: LOW-POWER MODES

Page 65

MC68HC705V8 Specification Rev. 2.1

Figure 8-2:

STOP/WAIT Flowcharts

8.1.2

WAIT INSTRUCTION

The WAIT instruction places the MCU in a low-power mode, which consumes more power

than the STOP Mode. In the WAIT Mode the internal processor clock is halted, suspending

all processor and internal bus activity. Internal timer clocks remain active, permitting

interrupts to be generated from the timer or a reset to be generated from the COP

Watchdog Timer. Execution of the WAIT instruction automatically clears the I-bit in the

Condition Code Register. All other registers, memory, and input/output lines remain in their

previous states.

MDLC

Bus

Edge?

Fetch Reset Vector

Service Interrupt

Stack

Set I-Bit

Vector to Interrupt Routine

WAIT

STOP MOR

bit set?

External

RESET?

IRQ

External

Interrupt?

Stop External Oscillator,

Stop Internal Timer Clock,

and Reset Startup Delay

Restart External Oscillator,

and Stabilization Delay

Stop Internal Processor Clock,

Clear I-Bit in CCR,

End

of Startup

Delay

IRQ

External

Interrupt?

External Oscillator Active,

and Internal

Timer Clock Active

Restart

Internal Processor Clock

Stop Internal Processor Clock,

Clear I-Bit in CCR,

TIMER

Internal

Interrupt?

External

RESET?

STOP

MDLC

Bus

Edge?

Port A

or C Falling

Edge?

Port A

or C Falling

Edge?

Reset Chip

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705V8GRS/D Datasheet(PDF) 76 Page - NXP Semiconductors

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