Electronic Components Datasheet Search
  British  ▼
ALLDATASHEET.CO.UK

X  

5P49V5929 Datasheet(PDF) 7 Page - Renesas Technology Corp

Part # 5P49V5929
Description  Programmable Clock Generator
PDF  27 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

5P49V5929 Datasheet(HTML) 7 Page - Renesas Technology Corp

Back Button 5P49V5929 Datasheet HTML 3Page - Renesas Technology Corp 5P49V5929 Datasheet HTML 4Page - Renesas Technology Corp 5P49V5929 Datasheet HTML 5Page - Renesas Technology Corp 5P49V5929 Datasheet HTML 6Page - Renesas Technology Corp 5P49V5929 Datasheet HTML 7Page - Renesas Technology Corp 5P49V5929 Datasheet HTML 8Page - Renesas Technology Corp 5P49V5929 Datasheet HTML 9Page - Renesas Technology Corp 5P49V5929 Datasheet HTML 10Page - Renesas Technology Corp 5P49V5929 Datasheet HTML 11Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 27 page
background image
FEBRUARY 21, 2019
7
PROGRAMMABLE CLOCK GENERATOR
5P49V5929 DATASHEET
Example 1
: The crystal load capacitance is specified as 8pF
and the stray capacitance at each crystal pin is Cs=1.5pF.
Assuming equal capacitance value at XIN and XOUT, the
equation is as follows:
8pF = (9pF + 0.5pF × XTAL[5:0] + 1.5pF) / 2
0.5pF × XTAL[5:0] = 5.5pF
→ XTAL[5:0] = 11 (decimal)
Example 2
: The crystal load capacitance is specified as 12pF
and the stray capacitance Cs is unknown. Footprints for
external capacitors Ce are added and a worst case Cs of 5pF
is used. For now we use Cs + Ce = 5pF and the right value for
Ce can be determined later to make 5pF together with Cs.
12pF = (9pF + 0.5pF × XTAL[5:0] + 5pF) / 2
XTAL[5:0] = 20 (decimal)
Manual Switchover Mode
When SM[1:0] is “0x”, the redundant inputs are in manual
switchover mode. In this mode, CLKSEL pin is used to switch
between the primary and secondary clock sources. The
primary and secondary clock source setting is determined by
the PRIMSRC bit. During the switchover, no glitches will occur
at the output of the device, although there may be frequency
and phase drift, depending on the exact phase and frequency
relationship between the primary and secondary clocks.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com