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9VRS4818B Datasheet(PDF) 8 Page - Renesas Technology Corp

Part # 9VRS4818B
Description  FUSION II CLOCK GENERATOR
PDF  21 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

9VRS4818B Datasheet(HTML) 8 Page - Renesas Technology Corp

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9VRS4818B
FUSION II CLOCK GENERATOR
IDT® FUSION II CLOCK GENERATOR
8
9VRS4818B
REV A 062512
Electrical Characteristics–Input/Supply/Common Output Parameters
PARAMETER
SYMBOL
CONDITIONS*
MIN
TYP
MAX
UNITS
Notes
I/O Supply Voltage
VDDxxx_LIO
-
0.9975
1.05
1.1025
V
1
1.5V Core Supply
Voltage
VDDxxx_1.5
-
1.425
1.5
1.575
V
1
3.3V Core Supply
Voltage
VDDxxx_3.3
-
3.135
3.3
3.465
V
1
Input High Voltage
VIH
3.3V Inputs
2
VDD + 0.3
V
1, 3
Input Low Voltage
VIL
3.3V inputs
VSS - 0.3
0.8
V
1, 3
Input High Current
IIH
VIN = VDD
-5
5
uA
1
IIL1
VIN = 0 V; Inputs with no
pull-up resistors
-5
uA
1
IIL2
VIN = 0 V; Inputs with pull-
up resistors
-200
uA
1
IDD_3.3SUSP
10
mA
1
IDD_1.5SUSP
1mA
1
IDD_I/OSUSP
1mA
1
IDD_3.3PD
2mA
1
IDD_1.5PD
1mA
1
IDD_I/OPD
0.1
mA
1
IDD_3.3
30
mA
1
IDD_1.5
30
mA
1
IDD_I/O
70
mA
1
Input Frequency
Fi
VDD = 3.3 V +/-5%
25.00
MHz
2
Pin Inductance
Lpin
7nH
1
CIN
Logic Inputs
5
pF
1
COUT
Output pin capacitance
6
pF
1
CINX
X1 & X2 pins
5
pF
1
Clk Stabilization
TSTAB
From VDD Power-Up to 1st
clock
1.8
ms
1
Modulation Frequency
Triangular Modulation
31
31.500
32
kHz
1
Tdrive_PD
SATA_DISP output enable
after
PD de-assertion
300
us
1
Tfall_PD
PD fall time of
5
ns
1
Trise_PD
PD rise time of
5
ns
1
SMBus Voltage
VDDSMB
2.7
5.5
V
1
Low-level Output Voltage
VOLSMB
@ IPULLUP
0.4
V
1
Current sinking at
VOL = 0.4 V
IPULLUPSMB
46
mA
1
SMBCLK/SMBDAT
Clock/Data Rise Time
TRSMB
(Max VIL - 0.15) to
(Min VIH + 0.15)
1000
ns
1
SMBCLK/SMBDAT
Clock/Data Fall Time
TFSMB
(Min VIH + 0.15) to
(Max VIL - 0.15)
300
ns
1
*TA = 0 - 70°C; All Supply Voltages at nominal+/-5%
1Guaranteed by design and characterization, not 100% tested in production.
2 Input frequency should be measured at the 25M output pin and tuned to ideal 25MHz to meet ppm frequency accuracy on PLL outputs.
3 CLKREQ# Inputs are 3.3V tolerant
all outputs driven
Input Low Current
Suspend Current
WOL_STOP (25M)
Enabled in Power Down
Power Down Current
WOL_STOP (25M)
Disabled in Power down
Operating Current
Input Capacitance



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