9VRS4818B

FUSION II CLOCK GENERATOR

IDT® FUSION II CLOCK GENERATOR

9

9VRS4818B

REV A 062512

AC Electrical Characteristics–Low-Power DIF Outputs: SATA_DISP and SRC

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

SRC/SATA Frequency

fSRC_SATA

Spread Specturm Off

100

MHz

1,6

Long Term Accuracy

ppm

Spread Specturm Off

-100

0

+100

ppm

1,6

Rising Edge Slew Rate

tSLR

Differential Measurement

0.6

3.5

4

V/ns

1,2

Falling Edge Slew Rate

tFLR

Differential Measurement

0.6

3.5

4

V/ns

1,2

Slew Rate Variation

tSLVAR

Single-ended Measurement

10

20

%

1

Maximum Output

Voltage

VHIGH

Includes overshoot

925

1150

mV

1

Minimum Output Voltage

VLOW

Includes undershoot

-300

-50

mV

1

Differential Voltage

Swing

VSWING

Differential Measurement

300

1950

mV

1

Crossing Point Voltage

VXABS

Single-ended Measurement

300

445

550

mV

1,3,4

Crossing Point Variation

VXABSVAR

Single-ended Measurement

28

140

mV

1,3,5

Duty Cycle

tdCYC

Differential Measurement

47

50

53

%

1

Jitter - Cycle to Cycle

tjCYC-CYC

Differential Measurement

55

125

ps

1

SRC[11:0] Skew Even

Outputs

tSRCSKEW_E

Differential Measurement

46

200

ps

1,8

SRC[11:0] Skew Odd

Outputs

tSRCSKEW_O

Differential Measurement

60

200

ps

1,8

SRC[11:0] Even to Odd

Skew

tSRCSKEW

Differential Measurement

1.925

ns

1,8

Jitter - SSC Residual

tSSC_RES

Differential Measurement

10

75

ps

1

PCIe Gen 1 specs

(1.5 - 22 MHz)

38

86

ps

1, 7

PCIe Gen 2 (8-16 MHz, 5-

16 MHz)

Lo-band content

(10kHz to 1.5MHz)

1.5

3

ps rms

1, 7

PCIe Gen 2 (8-16 MHz, 5-

16 MHz)

Hi-band content

(1.5MHz to Nyquist)

2.4

3.1

ps rms

1, 7

Default Spread when

enabled

-0.49

%

1, 9

Spread Option 1

-0.48

%

1, 9

Spread Option 2

-0.47

%

1, 9

Spread Option 3

-0.46

%

1, 9

*TA = 0 - 70°C; All Supply Voltages at nominal+/-5%

1Guaranteed by design and characterization, not 100% tested in production.

2 Slew rate measured through Vswing centered around differential zero

3 Vxabs is defined as the voltage where CLK = CLK#

4 Only applies to the differential rising edge (CLK rising and CLK# falling)

6 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that 25MHz output is at 25MHz

7 Applicable to all SRC outputs. See http://www.pcisig.com for complete specs. Guaranteed by design/characterization, not tested in production.

9 Only applies to SRC outputs. SATA_DISP outputs do not spread.

Jitter, Phase

tjphase

SSC

tjphaseSRC

5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and falling edge of

CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#.

8 SRC outputs are divided into two banks, odd and even. The odd bank skew window is 200 ps. The even bank skew window is 200ps. The

skew between the even and odd banks is intentionally set at 1.925 ns.