Table 9. Serial interface timings (VDD = 5 V; VCC = 24 V; -40 °C < TJ < 125 °C)

Symbol

Parameter

Test conditions

Min. Typ. Max.

Unit

fCLK

SPI clock frequency

20

MHz

TCLK

SPI clock period

50

ns

tr(CLK) tf(CLK)

SPI clock rise/fall time (see Figure 7, Figure 8)

5

ns

tsu(SS)

SS setup time (see Figure 7, Figure 8)

80

ns

th(SS)

SS hold time (see Figure 7, Figure 8)

80

ns

tc(SS)

SS disable time (see Figure 7, Figure 8)

20

μs

tw(CLK)

CLK high time (see Figure 7, Figure 8)

15

ns

tsu(SDI)

Data input setup time (see Figure 7, Figure 8)

6

ns

th(SDI)

Data input hold time (see Figure 7, Figure 8)

6

ns

ta(SDO)

Data output access time (see Figure 7, Figure 8)

RPULL-DOWN = 300 Ω

CLOAD = 50 pF

25

ns

tdis(SDO)

Data output disable time (see Figure 7, Figure 8)

20

ns

tv(SDO)

Data output valid time (see Figure 7, Figure 8)

20

ns

tJITTER

Jitter on single channel tCYCLE ( SS) = 20 μs

6

μs

Jitter on single channel tCYCLE ( SS) < 20 μs

20

Table 10. Internal communication timings (VDD = 5 V; VCC = 24 V; -40 °C < TJ < 125 °C)

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

frefresh

Refresh delay

15

kHz

tWD

Watchdog time

272

320

400

μs

Table 11. Insulation and safety-related specifications

Symbol

Parameter

Test conditions

Value Unit

CLR(1)

Clearance (minimum external air gap)

Measured from input terminals to output terminals,

shortest distance through air

2.6

mm

CPG(1) Creepage (minimum external tracking)

Measured from input terminals to output terminals,

shortest distance path along body

2.6

mm

CTI(2)

Comparative tracking index (tracking

resistance)

≥400

V

Isolation group

Material group

II

-

1. Creepage and clearance requirements should be applied according to the specific equipment isolation standard of an

application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the

mounting pads of the isolator on the PCB do not reduce this distance.

2. When high voltage is applied across the isolator, electric discharges on or close to the surface of the package, can cause

localized deterioration in the mold compound, resulting in a partially conducting path from one side of the isolator to the

other. This phenomenon is called tracking. The ability of a material to withstand tracking is quantified by a comparative

tracking index (CTI). Using a mold compound with a higher CTI allows the use of smaller packages and saves board space.

ISO808A, ISO808A-1

Electrical characteristics

DS14170 - Rev 1

page 12/38