6

Functional description

6.1

Serial interface

An integrated SPI peripheral provides a fast communication interface between an external micro-controller and

the IC purposing to drive ON/OFF the Power Stage outputs. Daisy chaining is allowed.

It follows the timing requirement established by the synchronous serial communication standard and works up to

20 MHz communication speed.

The communication implemented expects 8-bit data communication; the frame sent by the micro-controller only

contains the status of the channels (ON or OFF), while the frame received by the micro-controller is all "0" if no

fault event is triggered or all "1" if at least one fault has been triggered on the output stage.

Table 14. SDI frame

MSB

LSB

IN7

IN6

IN5

IN4

IN3

IN2

IN1

IN0

Table 15. SDO frame

MSB

LSB

0

0

0

0

0

0

0

0

6.2

Serial data in (SDI)

This pin is the IC input of the serial command frame (MOSI). SDI is reading on CLK rising edges and , thus, the

micro-controller must change SDI state during the CLK falling edges.

The bits sent through the SDI line are shifted in the internal Output Status Register. In daisy chaining

communication, the micro-controller keeps the SS low after the 8th bit to allow the shift of the Output Status

Register to the SDO line. The bits in the Output Status Register are frozen by the internal logic when the SS goes

high.

6.3

Serial data out (SDO)

This pin is the IC output of the serial fault frame (MISO). The information on SDO is updated on CLK falling

edges, whereas the micro-controller reads the SDO frame on CLK rising edges, as established by standard. At

communication start-up, when the SS falling edge is coming, only the first bit of the frame is just available.

SDO pin is tri-stated when the SS signal is high.

In daisy chaining communication the SDO line will transfer the content of the internal Output Status Register after

the 8th CLK pulse.

6.4

Serial data clock (CLK)

The CLK line is the IC input clock for serial data sampling. SDO is updated on CLK falling edges, and then

sampled on the rising edge. The SDI line is sampled on SCK rising edges.

When the SS signal is high (slave not selected), the micro-controller should drive the CLK low (settings for MCU

SPI port are CPHA = 0 and CPOL = 0).

6.5

Slave select (SS)

The slave select SS signal is used to enable the serial communication shift register. Data is flushed in through

the SDI pin and out from the SDO pin only when the SS pin is low. On the SS pin falling edge, the Fault Register

(containing IC fault conditions) is frozen, so any changing on the channel status will be latched until the next SS

falling edge event, the SDO is enabled and the internal refresh is disabled too. On the SS pin rising edge event,

the 8 bits in the Output Status Register are frozen and the outputs of the Process Stage are driven accordingly.

If more than 8 bits are flushed into the IC, only the last 8 are evaluated, the other ones are flushed out from the

SDO pin after fault condition bits. In this way a proper communication is granted in a daisy chain configuration.

ISO808A, ISO808A-1

Functional description

DS14170 - Rev 1

page 14/38