MPC940L Datasheet

4

©2016 Integrated Device Technology, Inc.

Revision 9, October 4, 2016

OBSOLETE

Table 5. DC Characteristics (TA = 0 to 70C, VCCI = 3.3 V ±5%; VCCO = 2.5 V ±5%)

Symbol

Characteristic

Min

Typ

Max

Unit

Condition

VIH

Input HIGH Voltage

CMOS_CLK

2.4

VCCI

V

VIL

Input LOW Voltage

CMOS_CLK

0.8

V

VPP

Peak-to-Peak Input Voltage

PECL_CLK

500

1000

mV

VCMR

Common Mode Range

PECL_CLK

VCCI – 1.4

VCCI – 0.6

V

VOH

Output HIGH Voltage

1.8

V

IOH = –12 mA

VOL

Output LOW Voltage

0.5

V

IOL = 12 mA

IIN

Input Current

200

A

CIN

Input Capacitance

4.0

pF

Cpd

Power Dissipation Capacitance

10

pF

per output

ZOUT

Output Impedance

23



ICC

Maximum Quiescent Supply Current

0.5

1.0

mA

Table 6. AC Characteristics (TA = 0 to 70C, VCCI = 3.3 V ±5%; VCCO = 2.5 V ±5%)

Symbol

Characteristic

Min

Typ

Max

Unit

Condition

Fmax

Maximum Input Frequency

250

MHz

tPLH

Propagation Delay

PECL_CLK

 150 MHz

CMOS_CLK

 150 MHz

2.0

1.7

2.8

2.5

3.5

3.0

ns

tPLH

Propagation Delay

PECL_CLK > 150 MHz

CMOS_CLK > 150 MHz

2.0

1.8

2.9

2.5

3.8

3.3

ns

tsk(o)

Output-to-Output Skew

PECL_CLK

CMOS_CLK

150

150

ps

tsk(pp)

Part-to-Part Skew

PECL_CLK

 150 MHz

CMOS_CLK

 150 MHz

1.5

1.3

ns

Note (1)

1. Across temperature and voltage ranges. Includes output skew.

tsk(pp)

Part-to-Part Skew

PECL_CLK > 150 MHz

CMOS_CLK > 150 MHz

1.8

1.5

ns

Note (1)

tsk(pp)

Part-to-Part Skew

PECL_CLK

CMOS_CLK

850

750

ps

Note (2)

2. For specific temperature and voltage. Includes output skew.

DC

Output Duty Cycle

fCLK < 134 MHz

fCLK  250 MHz

45

40

50

50

55

60

%

%

Input DC = 50%

Input DC = 50%

tr, tf

Output Rise/Fall Time

0.3

1.2

ns

0.5 – 1.8 V