HC05RC17GRSSLASHD datasheet(52/128 Pages) NXP

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Resets

General Release Specification

MC68HC05RC17 — Rev. 2.0

Resets

5.5.2.4 COP Watchdog Timer Considerations

The COP watchdog timer is active in all modes of operation if enabled

by a mask option. If the COP watchdog timer is selected by a mask

option, any execution of the STOP instruction (either intentionally or

inadvertently due to the CPU being disturbed) causes the oscillator to

halt and prevents the COP watchdog timer from timing out. If the COP

watchdog timer is selected by a mask option, the COP resets the MCU

when it times out. Therefore, it is recommended that the COP watchdog

be disabled for a system that must have intentional uses of the wait

mode for periods longer than the COP time out period.

The recommended interactions and considerations for the COP

watchdog timer, STOP instruction, and WAIT instruction are

summarized in Table 5-1.

Table 5-1. COP Watchdog Timer Recommendations

IF the Following Conditions Exist:

THEN the COP Watchdog Timer

Should Be:

Wait Time

Wait Time Less than COP Time Out

Enable or Disable COP by Mask Option

Wait Time More than COP Time Out

Disable COP by Mask Option

Any Length Wait Time

Disable COP by Mask Option

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC05RC17GRS/D Datasheet(PDF) 52 Page - NXP Semiconductors