PCF5271CVM100 datasheet(47/56 Pages) FREESCALE

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Preliminary Electrical Characteristics

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2

Freescale Semiconductor

Figure 14 shows timing for the values in Table 35 and Table 36.

Figure 14. I2C Input/Output Timings

8.10 Fast Ethernet AC Timing Specifications

MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.

8.10.1 MII Receive Signal Timing (ERXD[3:0], ERXDV, ERXER, and

ERXCLK)

The receiver functions correctly up to a ERXCLK maximum frequency of 25 MHz +1%. There is no

minimum frequency requirement. In addition, the processor clock frequency must exceed twice the

ERXCLK frequency.

Table 37 lists MII receive channel timings.

I7 1

Data setup time

—

tcyc

I8 1

Start condition setup time (for repeated start

condition only)

—

tcyc

I9 1

Stop condition setup time

—

tcyc

NOTES:

Note: Output numbers depend on the value programmed into the IFDR; an IFDR

programmed with the maximum frequency (IFDR = 0x20) results in minimum output

timings as shown in Table 36. The I2C interface is designed to scale the actual data

transition time to move it to the middle of the I2C_SCL low period. The actual position is

affected by the prescale and division values programmed into the IFDR; however, the

numbers given in Table 36 are minimum values.

Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can

only actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on

external signal capacitance and pull-up resistor values.

Specified at a nominal 50-pF load.

Table 36. I2C Output Timing Specifications between I2C_SCL and I2C_SDA (continued)

Num

Characteristic

Min

Max

Units

I2C_SCL

I2C_SDA

PCF5271CVM100 Datasheet(PDF) 47 Page - Freescale Semiconductor, Inc

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