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M25P64-VMF6TP Datasheet(PDF) 42 Page - STMicroelectronics |
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M25P64-VMF6TP Datasheet(HTML) 42 Page - STMicroelectronics |
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42 / 49 page  DC and AC parameters M25P64 42/49 1. tCH + tCL must be greater than or equal to 1/ fC(max) 2. Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. 5. When using the Page Program (PP) instruction to program consecutive Bytes, optimized timings are obtained with one sequence including all the Bytes versus several sequences of only a few Bytes. (1 ≤n ≤256). 6. VPPH should be kept at a valid level until the program or erase operation has completed and its result (success or failure) is known. Table 14. AC characteristics Test conditions specified in Table 10 and Table 11 Symbol Alt. Parameter Min. Typ. Max. Unit fC fC Clock Frequency for the following instructions: FAST_READ, PP, SE, BE, RES, WREN, WRDI, RDID, RDSR, WRSR D.C. 50 MHz fR Clock Frequency for READ instructions D.C. 20 MHz tCH (1) tCLH Clock High Time 9 ns tCL (1) tCLL Clock Low Time 9 ns tCLCH (2) Clock Rise Time(3) (peak to peak) 0.1 V/ns tCHCL (2) Clock Fall Time(3) (peak to peak) 0.1 V/ns tSLCH tCSS S Active Setup Time (relative to C) 5 ns tCHSL S Not Active Hold Time (relative to C) 5 ns tDVCH tDSU Data In Setup Time 2 ns tCHDX tDH Data In Hold Time 5 ns tCHSH S Active Hold Time (relative to C) 5 ns tSHCH S Not Active Setup Time (relative to C) 5 ns tSHSL tCSH S Deselect Time 100 ns tSHQZ (2) tDIS Output Disable Time 8 ns tCLQV tV Clock Low to Output Valid 8 ns tCLQX tHO Output Hold Time 0 ns tHLCH HOLD Setup Time (relative to C) 5 ns tCHHH HOLD Hold Time (relative to C) 5 ns tHHCH HOLD Setup Time (relative to C) 5 ns tCHHL HOLD Hold Time (relative to C) 5 ns tHHQX (2) tLZ HOLD to Output Low-Z 8 ns tHLQZ (2) tHZ HOLD to Output High-Z 8 ns tWHSL (4) Write Protect Setup Time 20 ns tSHWL (4) Write Protect Hold Time 100 ns tVPPHSL (6) Enhanced Program Supply Voltage High to Chip Select Low 200 ns tW Write Status Register Cycle Time 5 15 ms tPP (5) Page Program Cycle Time (256 Bytes) 1.4 5ms Page Program Cycle Time (n Bytes) 0.4+ n*1/256 Page Program Cycle Time (VPP = VPPH) (256 Bytes) 0.35 ms tSE Sector Erase Cycle Time 1 3 s Sector Erase Cycle Time (VPP = VPPH)0.5 s tBE Bulk Erase Cycle Time 68 160 s Bulk Erase Cycle Time (VPP = VPPH)35 160 s |
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