M25P64-VMF6TP datasheet(48/49 Pages) STMICROELECTRONICS

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Revision history

M25P64

48/49

Revision history

Table 18.

Document revision history

Date

Revision

Changes

28-Apr-2003

0.1

Target Specification Document written in brief form

15-May-2003

0.2

Target Specification Document written in full

20-Jun-2003

0.3

8x6 MLP8 and SO16(300 mil) packages added

18-Jul-2003

0.4

tPP, tSE and tBE revised

02-Sep-2003

0.5

Voltage supply range changed

19-Sep-2003

0.6

Table of contents, warning about exposed paddle on MLP8, and Pb-free

options added

17-Dec-2003

0.7

Value of tVSL(min) VWI, tPP(typ) and tBE(typ) changed. MLP8 package

removed.

15-Nov-2004

1.0

Document status promoted from Target Specification to Preliminary Data.

8x6 MLP8 package added. Minor wording changes.

24-Feb-2005

2.0

Deep Power-Down mode removed from datasheet (Figure 18: Read

Electronic Signature (RES) instruction sequence and data-out sequence

modified and tRES1 and tRES2 removed from Table 14: AC

characteristics). SO16 Wide package specifications updated. End timing

line of tSHQZ modified in Figure 24: Output timing. Figures moved below

the corresponding instructions in the Instructions section.

23-Dec-2005

3.0

Updated Page Program (PP) instructions in Page Programming, Page

Program (PP) and Table 14: AC characteristics.

Fast Program/Erase mode added and Power-up specified for Fast

Program/Erase mode in Power-up and Power-down section. W pin

changed to W/VPP. (see Write Protect/Enhanced Program supply voltage

(W/VPP) description). Note 2 inserted below Figure 26 Blank option

removed under Plating Technology.

tVPPHSL added to Table 14: AC characteristics and Figure 25: VPPH timing

inserted.

All packages are ECOPACK® compliant.

Document status promoted from Preliminary Data to full Datasheet

status.

16-Feb-2006

4.0

VDFPN8 (MLP8) package specifications updated (see Section 11:

Package mechanical).

07-Sep-2006

Figure 4: Bus master and memory devices on the SPI bus modified.

ICC1 maximum value updated in Table 13: DC characteristics.

19-Jan-2007

Hardware Write Protection feature added to Features on page 1.

VCC supply voltage and VSS ground descriptions added.

Figure 4: Bus master and memory devices on the SPI bus updated and

explanatory paragraph added.

At Power-up The Write In Progress (WIP) bit is reset.

VIO max modified and TLEAD added in Table 9: Absolute maximum

ratings. Small text changes.

Note 1 added to Table 15: VDFPN8 (MLP8) 8-lead Very thin Dual Flat

Package No lead, 8 × 6 mm, package mechanical data.

M25P64-VMF6TP Datasheet(PDF) 48 Page - STMicroelectronics

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