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DS20005045D-page 8

SST25VF080B

4.4.1

READ (25 MHZ)

The Read instruction, 03H, supports up to 25 MHz

Read. The device outputs the data starting from the

specified address location. The data output stream is

continuous through all addresses until terminated by a

low to high transition on CE#. The internal address

pointer will automatically increment until the highest

memory address is reached. Once the highest memory

address is reached, the address pointer will automati-

cally increment to the beginning (wrap-around) of the

address space. Once the data from address location

FFFFFH has been read, the next output will be from

address location 00000H.

The Read instruction is initiated by executing an 8-bit

command, 03H, followed by address bits [A23-A0]. CE#

must remain active-low for the duration of the Read

cycle. See Figure 4-3 for the Read sequence.

FIGURE 4-3:

READ SEQUENCE

Note 1: One bus cycle is eight clock periods.

2: Address bits above the most significant bit of each density can be VIL or VIH.

3: 4-Kbyte Sector Erase addresses: use AMS-A12, remaining addresses are “don’t care” but must be set

either at VIL or VIH.

4: 32-Kbyte Block Erase addresses: use AMS-A15, remaining addresses are “don’t care” but must be set

either at VIL or VIH.

5: 64-Kbyte Block Erase addresses: use AMS-A16, remaining addresses are “don’t care” but must be set

either at VIL or VIH.

6: To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed

by 2 bytes of data to be programmed. Data Byte 0 will be programmed into the initial address [A23-A1] with

A0 = 0, Data Byte 1 will be programmed into the initial address [A23-A1] with A0 = 1.

7: The Read STATUS Register is continuous with ongoing clock cycles until terminated by a low-to-high tran-

sition on CE#.

8: Manufacturer’s ID is read with A0 = 0, and Device ID is read with A0 = 1. All other address bits are 00H.

The Manufacturer’s ID and device ID output stream is continuous until terminated by a low-to-high transi-

tion on CE#.

TABLE 4-4:

DEVICE OPERATION INSTRUCTION

Instruction

Description

Op Code Cycle(1)

Address

Cycle(s)(2)

Dummy

Cycle(s)

Data

Cycle(s)

CE#

SO

SI

SCK

ADD.

0 1 234 5 6 78

ADD.

ADD.

03

H

15 16

23 24

31 32

39 40

70

47

48

55 56

63 64

N+2

N+3

N+4

N

N+1

DOUT

MS

MS

MS

MODE 0

MODE 3

DOUT

DOUT

DOUT

DOUT