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AT89C5132-ROTIL Datasheet(PDF) 6 Page - ATMEL Corporation |
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AT89C5132-ROTIL Datasheet(HTML) 6 Page - ATMEL Corporation |
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6 / 38 page ![]() 8 AT89C5132 4173CS–USB–07/04 Table 3. Timer 0 and Timer 1 Signal Description Table 4. Audio Interface Signal Description Table 5. USB Controller Signal Description Table 6. Signal Name Type Description Alternate Function INT0 I Timer 0 Gate Input INT0 serves as external run control for timer 0, when selected by GATE0 bit in TCON register. External Interrupt 0 INT0 input sets IE0 in the TCON register. If bit IT0 in this register is set, bit IE0 is set by a falling edge on INT0#. If bit IT0 is cleared, bit IE0 is set by a low level on INT0#. P3.2 INT1 I Timer 1 Gate Input INT1 serves as external run control for timer 1, when selected by GATE1 bit in TCON register. External Interrupt 1 INT1 input sets IE1 in the TCON register. If bit IT1 in this register is set, bit IE1 is set by a falling edge on INT1#. If bit IT1 is cleared, bit IE1 is set by a low level on INT1#. P3.3 T0 I Timer 0 External Clock Input When timer 0 operates as a counter, a falling edge on the T0 pin increments the count. P3.4 T1 I Timer 1 External Clock Input When timer 1 operates as a counter, a falling edge on the T1 pin increments the count. P3.5 Signal Name Type Description Alternate Function DCLK O DAC Data Bit Clock - DOUT O DAC Audio Data - DSEL O DAC Channel Select Signal DSEL is the sample rate clock output. - SCLK O DAC System Clock SCLK is the oversampling clock synchronized to the digital audio data (DOUT) and the channel selection signal (DSEL). - Signal Name Type Description Alternate Function D+ I/O USB Positive Data Upstream Port This pin requires an external 1.5 K Ω pull-up to V DD for full speed operation. - D- I/O USB Negative Data Upstream Port - |
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