P83C524 datasheet(36/76 Pages) PHILIPS

36 / 76 page

1997 Dec 15

Philips Semiconductors

Product speciﬁcation

8-bit microcontrollers

P83C524; P80C528; P83C528

Table 20 Description of the S1SCS bits

BIT

SYMBOL

FUNCTION

SDO/SDI

Serial Data Output and the ﬁltered Serial Data Input. SDI data is latched on the rising

edge of the ﬁltered serial clock. S1SCS.7 accesses the same memory locations as

S1BIT.7. Access of the data bit via S1SCS will not start an auto-clock pulse.

SCO/SCI

Serial Clock Output and the ﬁltered Serial Clock Input. Serial clock output SCO is

'OR-ed' with the auto-clock. If SCO = 1 the auto-clock output is inhibited. The internal

clock stretching logic and external devices can pull the SCL line LOW. If the auto-clock

is not used, the SCL line has to be controlled by setting SCO = 1, waiting for CLH = 1

and setting SCO = 0 after the speciﬁed SCL HIGH time. (Because of the input ﬁlter,

CLH will be set at least 8 XTAL clock periods after the SCL LOW-to-HIGH transition.)

CLH

Serial Clock LOW-to-HIGH transition ﬂag: set with a rising edge of the ﬁltered serial

clock. CLH = 1 indicates that, since the last CLH reset, a new valid data bit has been

latched in SDI. CLH can be reset by writing a 0 to S1SCS.5 or by a read/write of S1BIT.

Clearing CLH also clears RBF and WBF.

4BB

Bus Busy ﬂag: indicating that there has been a START condition that was not yet

followed by a STOP condition.

RBF

Read Bit Finished ﬂag: indicating a successful bit read.

RBF = 1 implies the following conditions:

CLH = 1: SCL had a rising edge

SCI = 0: the SCL pulse has finished

SI = 0: no START condition occurred

BB = 1: no STOP condition occurred

The RBF ﬂag can be cleared by clearing the CLH ﬂag.

WBF

Write Bit Finished ﬂag: indicating a successful bit write. The same conditions as for

RBF are true and also no 'arbitration loss' condition occurred. Arbitration is lost if a

1 data bit in SDO was over-ruled on SDA by an external device. The WBF ﬂag can be

cleared by clearing the CLH ﬂag.

STR

STRetch control ﬂag. STR = 1 enables stretching of all SCL LOW periods. This allows

the processor in I2C slave mode to react on a fast master. The STR ﬂag remains set

until cleared by writing a 0 to S1SCS.1.

The STretch (ST) ﬂag (not readable) pulls the serial clock LOW while ST = 1. The ST

ﬂag is set on the falling edge of the ﬁltered serial clock if STR = 1. It is also set after

reception of a START condition, regardless of the STR contents. ST is cleared with a

read or write of S1BIT.

ENS

ENable Serial I/O ﬂag. ENS = 1 enables the START detection and clock stretching

logic. ENS = 0 can be used to switch off the I2C-bus hardware. Note that the SDO and

SCO control ﬂags must be set to 1 before ENS is set to avoid pulling SCL or SDA lines

to 0.

P83C524 Datasheet(PDF) 36 Page - NXP Semiconductors

P83C524 Datasheet(HTML) 36 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

Datasheet Download

Link URL