IA88C00-PDW48I-R datasheet(25/80 Pages) INNOVASIC

25 / 80 page

IA88C00

Data Sheet

Microcontroller

As of Production Version -01

ENG 21 0 050519-00

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Innovasic Semiconductor

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When an interrupt in one of the 8 levels occurs and the corresponding mask bit is not set, the level bit of

the interrupt is set to 1. The interrupt structure contains 8 levels of interrupt, 16 vectors and 27 sources.

Interrupt priority is assigned by level and controlled by the Interrupt Priority Register (IPR)

ControlRegR255B0. Each level is masked (or enabled) according to the bits in the Interrupt Mask

levels of interrupts, IRQ register (SystemRegR220). When the corresponding bit in the Interrupt Mask

Figure 18. System Mode Register (SYM), R222

Bit

Not

Used

Not

Used

Not

Used

FIS2

FSI1

FSI0

FSE

GIE

Initial Value

Read/Write

R/W

The Fast Interrupt Select (FSI) selects which level interrupt can be treated as a fast interrupt. Fast

Interrupt Enable (FSE), when set to 1, enables the selected level for fast interrupt. Global Interrupt Enable

(GIE), when set to 1, enables interrupts in general.

Figure 19. Halt Mode Register (HMR), R223

Bit

Not

Used

Not

Used

Not

Used

Not

Used

Initial Value

Read/Write

R/W

D3 - CPU HALT mode - Writing a zero to this bit will invoke the HALT mode upon the execution of the

WFI instruction. The UART and counters can be halted only if D3 is 0. During HALT the internal CPU

clock is disabled, and no address strobe is generated. A hardware reset sets this bit to a 1.

D2 - Disable UART - Writing a zero to the bit will disable the UART. No interrupt request will be

generated. A 1 will make the UART and its interrupt logic remain active in HALT mode. A hardware

reset forces this bit to a 1.

D1 - Disable CT1 - Similar to CT0. When the counters are cascaded, the HALT mode 32-bit counter is

determined by the logical state of D1. A hardware reset forces this bit to a 1.

D0 - Disable CT0 - Writing a zero to this bit will disable the CT0 in HALT mode. No interrupt request

will be generated in this case. A 1 will keep the CT0 active. A hardware reset forces this bit to a 1.

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