IA88C00-PDW48I-R datasheet(58/80 Pages) INNOVASIC

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IA88C00

Data Sheet

Microcontroller

As of Production Version -01

ENG21 1 030617-04

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Interrupt Programming Model

The IA88C00 maintains program compatibility with the Super8. Enabling or disabling of interrupts are

controlled via the following registers:

Interrupt enable/disable. See the System Mode register (R222).

Level enable. See the interrupt Mask register (R221).

Level priority. See the Interrupt Priority register (R255, Bank 0).

Source enable/disable. Interrupt sources are enabled or disabled in the individual source’s Mode and

Control register.

Functional Overview

For an interrupt to be serviced, it’s source must be enabled. The corresponding interrupt and level must

likewise be enabled. Each interrupt input is conditioned with edge-triggered devices to convert all

interrupt inputs to “levels”. The eliminates the requirement for external hardware to maintain the interrupt

input prior to servicing.

When an interrupt source is received the processor is “vectored” to the vector address associated with the

interrupt. In the fact of multiple interrupts, the enabled interrupt whose level has the highest priority is

serviced first. For interrupts within the same level, the priority of the individual interrupt takes

precedence.

Upon servicing the interrupt, the processor clears the Interrupt Enable bit in the System Mode register to

prevent a high priority interrupt from disrupting the service routine. The program counter and status flags

are pushed onto the stack and the program counter is loaded with the appropriate interrupt vector and the

interrupt service routine (ISR) begins to the execute. Upon completion, the ISR executes an RET

instruction. The flags and program counter are popped off the stack and the Interrupt Enable bit in the

System Mode register is set.

The IA88C00 supports a special mode of “fast” interrupt processing. Utilization of this mode requires

program intervention. The vector address of the ISR must be loaded into the instruction pointer and the

Fast Interrupt enable bit in the System Mode Register must be set. Upon receipt of the interrupt source,

the ISR vector is loaded into the program counter while the old value of the program counter is saved in

the Instruction Pointer. Status flags are saved in the FLAGs register and the Fast interrupt Status Bit in

FLAGS is set. Upon completion of the ISR, the process is reversed.

Stack Operation

The IA88C00 maintains program model compatibility on all Stack operations. The stack may be

maintained in either the register file or in data memory space. For programming model details see

registers R216/R217 (the stack pointer) and register R254 (Memory Timing register)

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