TMS28F008AXY datasheet(13/52 Pages) TI

13 / 52 page

TMS28F008Axy,TMS28F800Axy

1 048 576 BY 8-BIT/524 288 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS851A – NOVEMBER 1997 – REVISED MARCH 1998

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

data protection

Data is secured or unsecured by using different combinations of the reset/deep power-down pin (RP), the write

protect pin (WP) and VPP supply levels. See to Table 2 for a listing of these combinations.

There are two configurations to secure the entire memory against inadvertant alteration of data. The VPP supply

pin can be held below the VPP lock-out voltage level (VPPLK) or the RP can be pulled to a logic-low level. If RP

is held low, the device resets, which means it powers down and, therefore, cannot be read. Typically, this pin

is tied to the system reset for additional protection during system power up.

The boot-block sector has an additional security feature through the WP pin. When the RP pin is at a logic-high

level, the WP pin controls whether the boot-block sector is protected. When WP is held at the logic-low level,

the boot block is protected. When WP is held at the logic-high level, the boot block is unprotected along with

the rest of the other sectors. Alternatively, the entire memory can be unprotected by pulling the RP pin to

VHH (12 V).

Table 2. Data-Protection Combinations (see Note 1)

DATA PROTECTION PROVIDED

VPP

All blocks locked

≤ VPPLK

All blocks locked (reset)

≥ VPPLK

VIL

All blocks unlocked

≥ VPPLK

VHH

Only boot block locked

≥ VPPLK

VIH

VIL

All blocks unlocked

≥ VPPLK

VIH

NOTE 1: For TMS28F008AZy and TMS28F800AZy (12-V VPP) products, the WP pin is

disabled and can be left floating. To unlock blocks, RP must be at VHH.

command-state machine (CSM)

Commands are issued to the CSM using standard microprocessor write timings. The CSM acts as an interface

between the external microprocessor and the internal WSM. Table 1 lists the CSM codes and device modes,

and Table 4 lists the data for the bus cycle. When a program or erase command is issued to the CSM, the WSM

controls the internal sequences and the CSM responds only to status reads. After the WSM completes its task,

the WSM status bit (SB7) is set to a 1, allowing the CSM to respond to the full command set again.

operation

Device operations are selected by entering standard JEDEC 8-bit command codes with conventional

microprocessor timing into an on-chip CSM through I/O pins DQ0–DQ7. When the device is powered up,

internal reset circuitry initializes the chip to a read-array mode of operation. Changing the mode of operation

requires that a command code be entered into the CSM. Table 1 lists the CSM codes for all modes of operation.

The on-chip status register allows the progress of various operations to be monitored. The status register is

interrogated by entering a read-status-register command into the CSM (cycle 1) and reading the register data

on I/O pins DQ0–DQ7 (cycle 2). Status-register bits SB0 through SB7 correspond to DQ0 through DQ7.

TMS28F008AXY Datasheet(PDF) 13 Page - Texas Instruments

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