MPC8280 datasheet(22/1386 Pages) FREESCALE

22 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

xxii

Freescale Semiconductor

Contents

Paragraph

Number

Title

Page

Number

14.4

Command Set............................................................................................................... 14-12

14.4.1

CP Command Register (CPCR)............................................................................... 14-12

14.4.1.1

CP Commands ..................................................................................................... 14-14

14.4.2

Command Register Example ................................................................................... 14-17

14.4.3

Command Execution Latency.................................................................................. 14-17

14.5

Dual-Port RAM............................................................................................................ 14-17

14.5.1

Buffer Descriptors (BDs)......................................................................................... 14-21

14.5.2

Parameter RAM ....................................................................................................... 14-21

14.6

RISC Timer Tables....................................................................................................... 14-23

14.6.1

RISC Timer Table Parameter RAM......................................................................... 14-23

14.6.2

RISC Timer Command Register (TM_CMD) ......................................................... 14-25

14.6.3

RISC Timer Table Entries........................................................................................ 14-25

14.6.4

RISC Timer Event Register (RTER)/Mask Register (RTMR) ................................ 14-25

14.6.5

set timer Command.................................................................................................. 14-26

14.6.6

RISC Timer Initialization Sequence ........................................................................ 14-26

14.6.7

RISC Timer Initialization Example ......................................................................... 14-27

14.6.8

RISC Timer Interrupt Handling ............................................................................... 14-27

14.6.9

RISC Timer Table Scan Algorithm.......................................................................... 14-27

14.6.10

Using the RISC Timers to Track CP Loading ......................................................... 14-28

Chapter 15

Serial Interface with Time-Slot Assigner

15.1

Features .......................................................................................................................... 15-3

15.2

Overview........................................................................................................................ 15-4

15.3

Enabling Connections to TSA ....................................................................................... 15-7

15.4

Serial Interface RAM ..................................................................................................... 15-8

15.4.1

One Multiplexed Channel with Static Frames ........................................................... 15-9

15.4.2

One Multiplexed Channel with Dynamic Frames ..................................................... 15-9

15.4.3

Programming SIx RAM Entries .............................................................................. 15-10

15.4.4

SIx RAM Programming Example............................................................................ 15-14

15.4.5

Static and Dynamic Routing .................................................................................... 15-15

15.5

Serial Interface Registers ............................................................................................. 15-17

15.5.1

SI Global Mode Registers (SIxGMR) ..................................................................... 15-17

15.5.2

SI Mode Registers (SIxMR) .................................................................................... 15-17

15.5.3

SIx RAM Shadow Address Registers (SIxRSR) ..................................................... 15-24

15.5.4

SI Command Register (SIxCMDR)......................................................................... 15-24

15.5.5

SI Status Registers (SIxSTR)................................................................................... 15-25

15.6

Serial Interface IDL Interface Support ........................................................................ 15-25

15.6.1

IDL Interface Example ............................................................................................ 15-26

15.6.2

IDL Interface Programming..................................................................................... 15-29

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