MPC8280 datasheet(58/1386 Pages) FREESCALE

58 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

lviii

Freescale Semiconductor

Figures

Figure

Number

Title

Page

Number

21-2

Two UART Multidrop Configurations.................................................................................. 21-7

21-3

Control Character Table ........................................................................................................ 21-8

21-4

Transmit Out-of-Sequence Register (TOSEQ) ................................................................... 21-10

21-5

Asynchronous UART Transmitter ...................................................................................... 21-11

21-6

Protocol-Specific Mode Register for UART (PSMR) ........................................................ 21-13

21-7

SCC UART Receiving using RxBDs.................................................................................. 21-16

21-8

SCC UART Receive Buffer Descriptor (RxBD) ................................................................ 21-17

21-9

SCC UART Transmit Buffer Descriptor (TxBD) ............................................................... 21-18

21-10

SCC UART Interrupt Event Example ................................................................................. 21-20

21-11

SCC UART Event Register (SCCE) and Mask Register (SCCM) ..................................... 21-20

21-12

SCC Status Register for UART Mode (SCCS) ................................................................... 21-21

22-1

HDLC Framing Structure...................................................................................................... 22-2

22-2

HDLC Address Recognition ................................................................................................. 22-4

22-3

HDLC Mode Register (PSMR)............................................................................................. 22-7

22-4

SCC HDLC Receive Buffer Descriptor (RxBD) .................................................................. 22-8

22-5

SCC HDLC Receiving Using RxBDs................................................................................. 22-11

22-6

SCC HDLC Transmit Buffer Descriptor (TxBD) ............................................................... 22-12

22-7

HDLC Event Register (SCCE)/HDLC Mask Register (SCCM) ........................................ 22-13

22-8

SCC HDLC Interrupt Event Example................................................................................. 22-15

22-9

CC HDLC Status Register (SCCS) ..................................................................................... 22-15

22-10

Typical HDLC Bus Multi-Master Configuration................................................................ 22-19

22-11

Typical HDLC Bus Single-Master Configuration............................................................... 22-20

22-12

Detecting an HDLC Bus Collision...................................................................................... 22-21

22-13

Nonsymmetrical Tx Clock Duty Cycle for Increased Performance ................................... 22-21

22-14

HDLC Bus Transmission Line Configuration .................................................................... 22-22

22-15

Delayed RTS Mode ............................................................................................................. 22-22

22-16

HDLC Bus TDM Transmission Line Configuration .......................................................... 22-23

23-1

Classes of BISYNC Frames .................................................................................................. 23-1

23-2

Control Character Table and RCCM..................................................................................... 23-6

23-3

BISYNC SYNC (BSYNC) ................................................................................................... 23-7

23-4

BISYNC DLE (BDLE) ......................................................................................................... 23-8

23-5

Protocol-Specific Mode Register for BISYNC (PSMR) .................................................... 23-10

23-6

SCC BISYNC RxBD .......................................................................................................... 23-12

23-7

SCC BISYNC Transmit BD (TxBD) .................................................................................. 23-14

23-8

BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM) ................................. 23-16

23-9

SCC Status Registers (SCCS) ............................................................................................. 23-16

24-1

Sending Transparent Frames between MPC8280s ............................................................... 24-4

24-2

SCC Transparent Receive Buffer Descriptor (RxBD) .......................................................... 24-8

24-3

SCC Transparent Transmit Buffer Descriptor (TxBD) ....................................................... 24-10

24-4

SCC Transparent Event Register (SCCE)/Mask Register (SCCM).................................... 24-11

24-5

SCC Status Register in Transparent Mode (SCCS) ............................................................ 24-12

MPC8280 Datasheet(PDF) 58 Page - Freescale Semiconductor, Inc

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