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TMP86CS49UG Datasheet(PDF) 39 Page - Toshiba Semiconductor |
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TMP86CS49UG Datasheet(HTML) 39 Page - Toshiba Semiconductor |
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39 / 252 page  Page 25 TMP86CS49UG 2.2.4.3 IDLE0 and SLEEP0 modes (IDLE0, SLEEP0) IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes. 1. Timing generator stops feeding clock to peripherals except TBT. 2. The data memory, CPU registers, program status word and port output latches are all held in the status in effect before IDLE0 and SLEEP0 modes were entered. 3. The program counter holds the address 2 ahead of the instruction which starts IDLE0 and SLEEP0 modes. Note: Before starting IDLE0 or SLEEP0 mode, be sure to stop (Disable) peripherals. Figure 2-12 IDLE0 and SLEEP0 Modes Yes (Normal release mode) Yes (Interrupt release mode) No Yes Reset input CPU and WDT are halted Reset TBT source clock falling edge TBTCR<TBTEN> = "1" Interrupt processing IMF = "1" Yes TBT interrupt enable No No No No Stopping peripherals by instruction Yes Starting IDLE0, SLEEP0 modes by instruction Execution of the instruction which follows the IDLE0, SLEEP0 modes start instruction |
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