TMP86CS49UG datasheet(32/252 Pages) TOSHIBA

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Page 18

2. Operational Description

2.2 System Clock Controller

TMP86CS49UG

2.2.4 Operating Mode Control

2.2.4.1 STOP mode

STOP mode is controlled by the system control register 1, the STOP pin input and key-on wakeup input

(STOP3 to STOP0) which is controlled by the STOP mode release control register (STOPCR).

The STOP pin is also used both as a port P20 and an INT5 (external interrupt input 5) pin. STOP mode is

started by setting SYSCR1<STOP> to “1”. During STOP mode, the following status is maintained.

1. Oscillations are turned off, and all internal operations are halted.

2. The data memory, registers, the program status word and port output latches are all held in the

status in effect before STOP mode was entered.

3. The prescaler and the divider of the timing generator are cleared to “0”.

4. The program counter holds the address 2 ahead of the instruction (e.g., [SET (SYSCR1).7])

which started STOP mode.

STOP mode includes a level-sensitive mode and an edge-sensitive mode, either of which can be

selected with the SYSCR1<RELM>. Do not use any key-on wakeup input (STOP3 to STOP0) for releas-

ing STOP mode in edge-sensitive mode.

Note 1: The STOP mode can be released by either the STOP or key-on wakeup pin (STOP3 to STOP0).

However, because the STOP pin is different from the key-on wakeup and can not inhibit the release

input, the STOP pin must be used for releasing STOP mode.

Note 2: During STOP period (from start of STOP mode to end of warm up), due to changes in the external

interrupt pin signal, interrupt latches may be set to “1” and interrupts may be accepted immediately

after STOP mode is released. Before starting STOP mode, therefore, disable interrupts. Also, before

enabling interrupts after STOP mode is released, clear unnecessary interrupt latches.

(1) Level-sensitive release mode (RELM = “1”)

In this mode, STOP mode is released by setting the STOP pin high or setting the STOP3 to STOP0

pin input which is enabled by STOPCR. This mode is used for capacitor backup when the main

power supply is cut off and long term battery backup.

Even if an instruction for starting STOP mode is executed while STOP pin input is high or STOP3

to STOP0 input is low, STOP mode does not start but instead the warm-up sequence starts immedi-

ately. Thus, to start STOP mode in the level-sensitive release mode, it is necessary for the program to

first confirm that the STOP pin input is low or STOP3 to STOP0 input is high. The following two

methods can be used for confirmation.

1. Testing a port.

2. Using an external interrupt input INT5 (INT5 is a falling edge-sensitive input).

Example 1 :Starting STOP mode from NORMAL mode by testing a port P20.

(SYSCR1), 01010000B

; Sets up the level-sensitive release mode

SSTOPH:

TEST

(P2PRD). 0

; Wait until the STOP pin input goes low level

JRS

F, SSTOPH

; IMF

← 0

SET

(SYSCR1). 7

; Starts STOP mode

TMP86CS49UG Datasheet(PDF) 32 Page - Toshiba Semiconductor

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