TMP86CS49UG datasheet(82/252 Pages) TOSHIBA

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Page 68

6. Watchdog Timer (WDT)

6.2 Watchdog Timer Control

TMP86CS49UG

6.2.3 Watchdog Timer Disable

To disable the watchdog timer, set the register in accordance with the following procedures. Setting the reg-

ister in other procedures causes a malfunction of the microcontroller.

1. Set the interrupt master flag (IMF) to “0”.

2. Set WDTCR2 to the clear code (4EH).

3. Set WDTCR1<WDTEN> to “0”.

4. Set WDTCR2 to the disable code (B1H).

Note:While the watchdog timer is disabled, the binary counters of the watchdog timer are cleared.

6.2.4 Watchdog Timer Interrupt (INTWDT)

When WDTCR1<WDTOUT> is cleared to “0”, a watchdog timer interrupt request (INTWDT) is generated

by the binary-counter overflow.

A watchdog timer interrupt is the non-maskable interrupt which can be accepted regardless of the interrupt

master flag (IMF).

When a watchdog timer interrupt is generated while the other interrupt including a watchdog timer interrupt

is already accepted, the new watchdog timer interrupt is processed immediately and the previous interrupt is

held pending. Therefore, if watchdog timer interrupts are generated continuously without execution of the

RETN instruction, too many levels of nesting may cause a malfunction of the microcontroller.

To generate a watchdog timer interrupt, set the stack pointer before setting WDTCR1<WDTOUT>.

Example :Disabling the watchdog timer

: IMF

← 0

(WDTCR2), 04EH

: Clears the binary counter

LDW

(WDTCR1), 0B101H

: WDTEN

← 0, WDTCR2 ← Disable code

Table 6-1 Watchdog Timer Detection Time (Example: fc = 16.0 MHz, fs = 32.768 kHz)

WDTT

Watchdog Timer Detection Time[s]

NORMAL1/2 mode

SLOW

mode

DV7CK = 0

DV7CK = 1

2.097

524.288 m

131.072 m

250 m

32.768 m

62.5 m

Example :Setting watchdog timer interrupt

SP, 083FH

: Sets the stack pointer

(WDTCR1), 00001000B

: WDTOUT

← 0

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