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STPM32 Datasheet(PDF) 52 Page - STMicroelectronics

Part # STPM32
Description  ASSP for metering applications with up to four independent 24-bit 2nd order sigma-delta ADCs, 4 MHz OSF and 2 embedded PGLNA
PDF  89 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STPM32 Datasheet(HTML) 52 Page - STMicroelectronics

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Table 31. Baud rate register examples
Baud rate
BRDIV
BRRI
BRRF
Register value
2400
416.666667
416 = 0x1A0
11 = 0xB
1A0B
9600
104.166667
104 = 0x68
3 = 0x3
683
19200
52.0833333
52 = 0x34
1 = 0x1
341
57600
17.3611111
17 = 0x11
6 = 0x6
116
115200
8.68055556
8 = 0x8
11 = 0xB
8B
230400
4.34027778
4 = 0x4
5 = 0x5
45
460800
2.17013889
2 = 0x2
3 = 0x3
23
8.6.4
UART/SPI status register and interrupt control register
At row 20, at read address 0x28, the register is responsible for holding the status of UART/SPI peripherals of the
STPM3x device. Setting the correspondent bit in IRQ CR the interrupt mask raises an interrupt on both INT1,
INT2 pins based on the peripheral status.
Table 32. UART/SPI status and interrupt control register
Register
Bit position
Description
Default value
Access mode
SR
30
SPI RX overrun
0
RW
29
SPITX underrun
0
RW
28
SPI CRC error
0
RW
27
UART/SPI write address error
0
RW
26
UART/SPI read address error
0
RW
25
SPITX empty
0
RO
24
SPI RX full
0
RO
22
UART TX overrun
0
RW
21
UART RX overrun
0
RW
20
UART noise error
0
RW
19
UART frame error
0
RW
18
UART timeout error
0
RW
17
UART CRC error
0
RW
16
UART break
0
RW
IRQ CR
14
mask for SPI RX overrun error status bit
0
RW
13
maskfor SPI TX underrun error status
bit
0
RW
12
mask for SPI CRC error status bit
0
RW
11
mask for write address error status bit
0
RW
10
mask for read address error status bit
0
RW
9
mask for SPITX empty
0
RW
8
mask for SPI RX full
0
RW
6
mask for UART TX overrun
0
RW
5
mask for UART RX overrun
0
RW
4
mask for UART noise error
0
RW
3
mask for UART frame error
0
RW
STPM32, STPM33, STPM34
Communication protocol
DS10272 - Rev 13
page 52/89



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