STPM32_V02 datasheet(37/89 Pages) STMICROELECTRONICS

37 / 89 page

Figure 42. Sag and swell detection blocks

Vx_SAG_start

SAG

SAGx_TIME[14:0]

SAG_THRx[9:0]

SAG_TIME_THR[13:0]

SWV_THRx[9:0]

SWV_EV[3:0]

SWV_TIME[14:0]

SWELL

SWC_THRx[9:0]

SWC_EV[3:0]

SWC_TIME[14:0]

ClearSS

Vx Fund[23:0]

SAGx_EV[3:0]

Vx_SAG_end

Vx Fund[23:0]

Cx Fund[23:0]

Vx_SWELL_start

Vx_SWELL_end

Cx_SWELL_start

Cx_SWELL_end

Voltage sag detection

To detect a voltage sag, the fundamental component of voltage is compared to the 10-bit threshold

SAG_THRx[9:0] in DSP_CR5 and DSP_CR7 for primary and secondary channel respectively.

An internal time counter is incremented until momentary voltage value is below the threshold. Sag event is

recorded when the timer counter reaches a programmable value set by SAG_TIME_THR[13:0] bits in DSP_CR3.

This time threshold is unique for both channels.

When a sag event is detected, LSB of SAGx_EV[3:0] event register and SAG_Start bit are set in the interrupt

status register and an interrupt is generated.

If sag event ceases, SAGx_EV register is left shifted and zero is added as LSB, besides, SAG_end bit in the

interrupt status register is set as well.

The duration of the event is stored in SAGx_TIME[14:0] in DSP_REG16 and DSP_REG18 for primary and

secondary voltage channel respectively.

If the overflow of SAG_TIME register occurs, SAGx_EV register is left shifted and its LSB is set, as shown in

Figure 43.

LSB of time registers is 8 μs.

To disable sag detection, the SAG_THRx register must be set to zero.

STPM32, STPM33, STPM34

Functional description of hardwired DSP

DS10272 - Rev 13

page 37/89

STPM32 Datasheet(PDF) 37 Page - STMicroelectronics

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