MPC8313E datasheet(72/92 Pages) FREESCALE

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Clocking

19.2

Core PLL Configuration

RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300

core clock (core_clk). Table 65 shows the encodings for RCWL[COREPLL]. COREPLL values that are

not listed in Table 65 should be considered as reserved.

NOTE

Core VCO frequency = Core frequency

× VCO divider. The VCO divider,

which is determined by RCWLR[COREPLL], must be set properly so that

the core VCO frequency is in the range of 400–800 MHz.

Low

0101

5 : 1

120

125

167

Low

0110

6 : 1

144

150

CFG_CLKIN_DIV select the ratio between SYS_CLK_IN and PCI_SYNC_OUT.

SYS_CLK_IN is the input clock in host mode; PCI_CLK is the input clock in agent mode.

Table 65. e300 Core PLL Configuration

RCWL[COREPLL]

core_clk : csb_clk Ratio 1

VCO divider (vcod) 2

0–1

2–5

0000

PLL bypassed

(PLL off,

csb_clk clocks core directly)

PLL bypassed

(PLL off,

csb_clk clocks core directly)

nnnn

nn/a

n/a

0001

01:1

0001

01:1

0001

01:1

0001

1.5:1

0001

1.5:1

0001

1.5:1

0010

02:1

0010

02:1

0010

02:1

0010

2.5:1

0010

2.5:1

0010

2.5:1

Table 64. CSB Frequency Options (continued)

CFG_CLKIN_DIV at reset 1

SPMF

csb_clk :Input Clock Ratio 2

Input Clock Frequency (MHz)2

33.33

66.67

csb_clk Frequency (MHz)

MPC8313E Datasheet(PDF) 72 Page - Freescale Semiconductor, Inc

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