MPC8313E datasheet(13/92 Pages) FREESCALE

13 / 92 page

MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

RESET Initialization

This section describes the DC and AC electrical specifications for the reset initialization timing and

electrical requirements of the MPC8313E.

5.1

RESET DC Electrical Characteristics

Table 9 provides the DC electrical characteristics for the RESET pins.

5.2

RESET AC Electrical Characteristics

Table 10 provides the reset initialization AC timing specifications.

SYS_CLK_IN/PCI_CLK rise and fall time

tKH, tKL

0.6

0.8

1.2

SYS_CLK_IN/PCI_CLK duty cycle

tKHK/tSYS_CLK_IN

—

SYS_CLK_IN/PCI_CLK jitter

—

±150

4, 5

Notes:

1. Caution: The system, core, security block must not exceed their respective maximum or minimum operating frequencies.

2. Rise and fall times for SYS_CLK_IN/PCI_CLK are measured at 0.4 V and 2.7 V.

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter—short term and long term—and is guaranteed by design.

5. The SYS_CLK_IN/PCI_CLK driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set

low to allow cascade-connected PLL-based devices to track SYS_CLK_IN drivers with the specified jitter.

Table 9. RESET Pins DC Electrical Characteristics

Characteristic

Symbol

Condition

Min

Max

Unit

Input high voltage

VIH

—2.1

NVDD +0.3

Input low voltage

VIL

—

–0.3

0.8

Input current

IIN

0 V

≤ VIN ≤ NVDD

±5

μA

Output high voltage

VOH

IOH = –8.0 mA

2.4

—

Output low voltage

VOL

IOL = 8.0 mA

—

0.5

Output low voltage

VOL

IOL = 3.2 mA

—

0.4

Table 10. RESET Initialization Timing Specifications

Parameter/Condition

Min

Max

Unit

Notes

Required assertion time of HRESET or SRESET (input) to activate reset flow

—

tPCI_SYNC_IN

Required assertion time of PORESET with stable clock and power applied to

SYS_CLK_IN when the device is in PCI host mode

—

tSYS_CLK_IN

Required assertion time of PORESET with stable clock and power applied to

PCI_SYNC_IN when the device is in PCI agent mode

—

tPCI_SYNC_IN

Table 8. SYS_CLK_IN AC Timing Specifications (continued)

MPC8313E Datasheet(PDF) 13 Page - Freescale Semiconductor, Inc

MPC8313E Datasheet(HTML) 13 Page - Freescale Semiconductor, Inc

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