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PSD913F2 Datasheet(PDF) 75 Page - STMicroelectronics |
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PSD913F2 Datasheet(HTML) 75 Page - STMicroelectronics |
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75 / 94 page  Preliminary Information PSD9XX Family 71 Microcontroller Interface – PSD9XX AC/DC Parameters (5V ± 10% Versions) -70 -90 -15 Symbol Parameter Conditions Min Max Min Max Min Max Unit tISCCF TCK Clock Frequency (except for PLD) (Note 1) 20 18 14 MHz tISCCH TCK Clock High Time (Note 1) 23 26 31 ns tISCCL TCK Clock Low Time (Note 1) 23 26 31 ns tISCCF-P TCK Clock Frequency (for PLD only) (Note 2) 2 2 2 MHz tISCCH-P TCK Clock High Time(for PLD only) (Note 2) 240 240 240 ns tISCCL-P TCK Clock Low Time(for PLD only) (Note 2) 240 240 240 ns tISCPSU ISC Port Set Up Time 7 8 10 ns tISCPH ISC Port Hold Up Time 5 5 5 ns tISCPCO ISC Port Clock to Output 21 23 25 ns tISCPZV ISC Port High-Impedance to Valid Output 21 23 25 ns tISCPVZ ISC Port Valid Output to High-Impedance 21 23 25 ns ISC Timing (5 V ± 10%) NOTES: 1. For “non-PLD” programming, erase or in ISC by-pass mode. 2. For program or erase PLD only. Symbol Parameter Min Typ Max Unit Flash Bulk Erase (Preprogrammed to 00) (Note 1) 3 30 sec Flash Bulk Erase (Not Preprogrammed) 5 sec tWHQV3 Sector Erase (Preprogrammed to 00) 1 30 sec tWHQV2 Sector Erase (Not Preprogrammed) 2.2 sec tWHQV1 Byte Program 14 1200 µs Program/Erase Cycles (Per Sector) 100,000 cycles tWHWLO Sector Erase Time-Out 100 µs tQ7VQV DQ7 Valid to Output (DQ7-0) Valid (Data Polling) (Note 2) 30 ns Flash Program, Write and Erase Times (5 V ± 10%) NOTE: 1. Programmed to all zeros before erase. 2. The polling status DQ7 is valid tQ7VQV ns before the data byte DQ0-7 is valid for reading. |
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