ST72104G datasheet(83/135 Pages) STMICROELECTRONICS

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ST72104G, ST72215G, ST72216G, ST72254G

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I2C BUS INTERFACE (Cont’d)

2C CLOCK CONTROL REGISTER (CCR)

Read / Write

Reset Value: 0000 0000 (00h)

Bit 7 = FM/SM

Fast/Standard I2C mode.

This bit is set and cleared by software. It is not

cleared when the interface is disabled (PE=0).

0: Standard I

2C mode

1: Fast I2C mode

Bit 6:0 = CC6-CC0

7-bit clock divider.

These bits select the speed of the bus (FSCL) de-

pending on the I2C mode. They are not cleared

when the interface is disabled (PE=0).

– Standard mode (FM/SM=0): FSCL <= 100kHz

FSCL =FCPU/(2x([CC6..CC0]+2))

– Fast mode (FM/SM=1): FSCL > 100kHz

FSCL =FCPU/(3x([CC6..CC0]+2))

Note: The programmed FSCL assumes no load on

SCL and SDA lines.

I2C DATA REGISTER (DR)

Read / Write

Reset Value: 0000 0000 (00h)

Bit 7:0 = D7-D0

8-bit Data Register.

These bits contain the byte to be received or trans-

mitted on the bus.

– Transmitter mode: Byte transmission start auto-

matically when the software writes in the DR reg-

ister.

– Receiver mode: the first data byte is received au-

tomatically in the DR register using the least sig-

nificant bit of the address.

Then, the following data bytes are received one

by one after reading the DR register.

FM/SM

CC6

CC5

CC4

CC3

CC2

CC1

CC0

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