ST72104G datasheet(54/135 Pages) STMICROELECTRONICS

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ST72104G, ST72215G, ST72216G, ST72254G

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16-BIT TIMER (Cont’d)

11.2.4 Low Power Modes

11.2.5 Interrupts

Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-

ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt

mask in the CC register is reset (RIM instruction).

11.2.6 Summary of Timer modes

1) See note 4 in Section 11.2.3.5 ”One Pulse Mode” on page 50

2) See note 5 in Section 11.2.3.5 ”One Pulse Mode” on page 50

3) See note 4 in Section 11.2.3.6 ”Pulse Width Modulation Mode” on page 52

Mode

Description

WAIT

No effect on 16-bit Timer.

Timer interrupts cause the device to exit from WAIT mode.

HALT

16-bit Timer registers are frozen.

In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous

count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter

reset value when the MCU is woken up by a RESET.

If an input capture event occurs on the ICAP

i pin, the input capture detection circuitry is armed. Consequent-

ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICF

i bit is set, and

the counter value present when exiting from HALT mode is captured into the IC

iR register.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

Input Capture 1 event/Counter reset in PWM mode

ICF1

ICIE

Yes

Input Capture 2 event

ICF2

Yes

Output Compare 1 event (not available in PWM mode)

OCF1

OCIE

Yes

Output Compare 2 event (not available in PWM mode)

OCF2

Yes

Timer Overflow event

TOF

TOIE

Yes

MODES

AVAILABLE RESOURCES

Input Capture 1

Input Capture 2

Output Compare 1 Output Compare 2

Input Capture (1 and/or 2)

Yes

Output Compare (1 and/or 2)

Yes

One Pulse Mode

Not Recommended1)

Partially 2)

PWM Mode

Not Recommended3)

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