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ST72104G Datasheet(PDF) 93 Page - STMicroelectronics |
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ST72104G Datasheet(HTML) 93 Page - STMicroelectronics |
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93 / 135 page  ST72104G, ST72215G, ST72216G, ST72254G 93/135 12.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in the following table: Using a pre-byte The instructions are described with one to four bytes. In order to extend the number of available op- codes for an 8-bit CPU (256 opcodes), three differ- ent prebyte opcodes are defined. These prebytes modify the meaning of the instruction they pre- cede. The whole instruction becomes: PC-2 End of previous instruction PC-1 Prebyte PC opcode PC+1 Additional word (0 to 2) according to the number of bytes required to compute the ef- fective address These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent ad- dressing mode by a Y one. PIX 92 Replace an instruction using di- rect, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. It also changes an instruction using X indexed ad- dressing mode to an instruction using indirect X in- dexed addressing mode. PIY 91 Replace an instruction using X in- direct indexed addressing mode by a Y one. Load and Transfer LD CLR Stack operation PUSH POP RSP Increment/Decrement INC DEC Compare and Tests CP TNZ BCP Logical operations AND OR XOR CPL NEG Bit Operation BSET BRES Conditional Bit Test and Branch BTJT BTJF Arithmetic operations ADC ADD SUB SBC MUL Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP RET Conditional Branch JRxx Interruption management TRAP WFI HALT IRET Code Condition Flag modification SIM RIM SCF RCF |
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