H8SXSLASH1663 datasheet(1035/1158 Pages) RENESAS

1035 / 1158 page

Section 23 Power-Down Modes

Rev.1.00 Jun. 07, 2006 Page 983 of 1102

REJ09B0294-0100

23.7

Software Standby Mode

23.7.1

Transition to Software Standby Mode

If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby

mode is entered. In this mode, the CPU, on-chip peripheral functions, and oscillator all stop.

However, the contents of the CPU's internal registers, on-chip RAM data, and the states of on-chip

peripheral functions other than the SCI, and the states of the I/O ports, are retained. Whether the

address bus and bus control signals are placed in the high-impedance state or retain the output

state can be specified by the OPE bit in SBYCR. In this mode the oscillator stops, allowing power

consumption to be significantly reduced.

If the WDT is used as a watchdog timer, it is impossible to make a transition to software standby

mode. The WDT should be stopped before the SLEEP instruction execution.

23.7.2

Clearing Software Standby Mode

Software standby mode is cleared by an external interrupt (NMI pin, or pins

IRQ0 to IRQ11*),

internal interrupt (32K timer) or by means of the

RES pin or STBY pin.

1. Clearing by interrupt

When an NMI or IRQ0 to IRQ11* interrupt request signal is input, clock oscillation starts, and

after the elapse of the time set in bits STS4 to STS0 in SBYCR, stable clocks are supplied to

the entire LSI, software standby mode is cleared, and interrupt exception handling is started.

When clearing software standby mode with an IRQ0 to IRQ11* interrupt, set the

corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts

IRQ0 to IRQ11* is generated. Software standby mode cannot be cleared if the interrupt has

been masked on the CPU side or has been designated as a DTC activation source.

Note: * By setting the SSIn bit in SSIER to 1,

IRQ0 to IRQ11 can be used as a software

standby mode clearing source.

2. Clearing by

RES pin

When the

RES pin is driven low, clock oscillation is started. At the same time as clock

oscillation starts, clocks are supplied to the entire LSI. Note that the

RES pin must be held low

until clock oscillation settles. When the

RES pin goes high, the CPU begins reset exception

handling.

3. Clearing by

STBY pin

When the

STBY pin is driven low, a transition is made to hardware standby mode.

H8SX/1663 Datasheet(PDF) 1035 Page - Renesas Technology Corp

H8SX/1663 Datasheet(HTML) 1035 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL