H8SXSLASH1663 datasheet(1036/1158 Pages) RENESAS

1036 / 1158 page

Section 23 Power-Down Modes

Rev.1.00 Jun. 07, 2006 Page 984 of 1102

REJ09B0294-0100

23.7.3

Setting Oscillation Settling Time after Clearing Software Standby Mode

Bits STS4 to STS0 in SBYCR should be set as described below.

1. Using a crystal resonator

Set bits STS4 to STS0 so that the standby time is at least equal to the oscillation settling time.

Table 23.2 shows the standby times for operating frequencies and settings of bits STS4 to

STS0.

2. Using an external clock

A PLL circuit settling time is necessary. Refer to table 23.2 to set the standby time.

Table 23.2

Oscillation Settling Time Settings

φ* [MHz]

STS4 STS3 STS2 STS1 STS0

Standby

Time

Unit

Reserved



µs

Reserved



Reserved



Reserved



Reserved



1.8

2.6

3.2

512

14.6

20.5

25.6

1024

29.3

41.0

51.2

2048

58.5

81.9

102.4

4096

0.12

0.16

0.20

16384

0.47

0.66

0.82

32768

0.94

1.31

1.64

65536

1.87

2.62

3.28

131072

3.74

5.24

6.55

262144

7.49

10.49

13.11

524288

14.98

20.97

26.21

Reserved



: Recommended time setting when using an external clock.

: Recommended time setting when using a crystal resonator.

Note:

φ is the output from the peripheral module frequency divider.

H8SX/1663 Datasheet(PDF) 1036 Page - Renesas Technology Corp

H8SX/1663 Datasheet(HTML) 1036 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL