H8SXSLASH1663 datasheet(1047/1158 Pages) RENESAS

1047 / 1158 page

Section 24 List of Registers

Rev.1.00 Jun. 07, 2006 Page 995 of 1102

REJ09B0294-0100

Section 24 List of Registers

The register list gives information on the on-chip I/O register addresses, how the register bits are

configured, and the register states in each operating mode. The information is given as shown

below.

1. Register addresses (address order)

• Registers are listed from the lower allocation addresses.

• Registers are classified according to functional modules.

• The number of Access Cycles indicates the number of states based on the specified reference

clock. For details, refer to section 6.5.4, External Bus Interface.

• Among the internal I/O register area, addresses not listed in the list of registers are undefined

or reserved addresses. Undefined and reserved addresses cannot be accessed. Do not access

these addresses; otherwise, the operation when accessing these bits and subsequent operations

cannot be guaranteed.

2. Register bits

• Bit configurations of the registers are listed in the same order as the register addresses.

• Reserved bits are indicated by  in the bit name column.

• Space in the bit name field indicates that the entire register is allocated to either the counter or

data.

• For the registers of 16 or 32 bits, the MSB is listed first.

• Byte configuration description order is subject to big endian.

3. Register states in each operating mode

• Register states are listed in the same order as the register addresses.

• For the initialized state of each bit, refer to the register description in the corresponding

section.

• The register states shown here are for the basic operating modes. If there is a specific reset for

an on-chip peripheral module, refer to the section on that on-chip peripheral module.

H8SX/1663 Datasheet(PDF) 1047 Page - Renesas Technology Corp