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H8SX/1663 Datasheet(PDF) 1051 Page - Renesas Technology Corp |
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H8SX/1663 Datasheet(HTML) 1051 Page - Renesas Technology Corp |
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1051 / 1158 page  Section 24 List of Registers Rev.1.00 Jun. 07, 2006 Page 999 of 1102 REJ09B0294-0100 Register Name Abbreviation Number of Bits Address Module Data Width Access Cycles (Read/Write) Port H input buffer control register PHICR 8 H'FFBAC I/O port 8 2P φ/2Pφ Port I input buffer control register PIICR 8 H'FFBAD I/O port 8 2P φ/2Pφ Port D pull-up MOS control register PDPCR 8 H'FFBB4 I/O port 8 2P φ/2Pφ Port E pull-up MOS control register PEPCR 8 H'FFBB5 I/O port 8 2P φ/2Pφ Port F pull-up MOS control register PFPCR 8 H'FFBB6 I/O port 8 2P φ/2Pφ Port H pull-up MOS control register PHPCR 8 H'FFBB8 I/O port 8 2P φ/2Pφ Port I pull-up MOS control register PIPCR 8 H'FFBB9 I/O port 8 2P φ/2Pφ Port 2 open-drain control register P2ODR 8 H'FFBBC I/O port 8 2P φ/2Pφ Port F open-drain control register PFODR 8 H'FFBBD I/O port 8 2P φ/2Pφ Port function control register 0 PFCR0 8 H'FFBC0 I/O port 8 2P φ/3Pφ Port function control register 1 PFCR1 8 H'FFBC1 I/O port 8 2P φ/3Pφ Port function control register 2 PFCR2 8 H'FFBC2 I/O port 8 2P φ/3Pφ Port function control register 4 PFCR4 8 H'FFBC4 I/O port 8 2P φ/3Pφ Port function control register 6 PFCR6 8 H'FFBC6 I/O port 8 2P φ/3Pφ Port function control register 7 PFCR7 8 H'FFBC7 I/O port 8 2P φ/3Pφ Port function control register 9 PFCR9 8 H'FFBC9 I/O port 8 2P φ/3Pφ Port function control register B PFCRB 8 H'FFBCB I/O port 8 2P φ/3Pφ Port function control register C PFCRC 8 H'FFBCC I/O port 8 2P φ/3Pφ Software standby release IRQ enable register SSIER 16 H'FFBCE INTC 8 2P φ/3Pφ DMA source address register_0 DSAR_0 32 H'FFC00 DMAC_0 16 2I φ/2Iφ DMA destination address register_0 DDAR_0 32 H'FFC04 DMAC_0 16 2I φ/2Iφ DMA offset register_0 DOFR_0 32 H'FFC08 DMAC_0 16 2I φ/2Iφ DMA transfer count register_0 DTCR_0 32 H'FFC0C DMAC_0 16 2I φ/2Iφ DMA block size register_0 DBSR_0 32 H'FFC10 DMAC_0 16 2I φ/2Iφ DMA mode control register_0 DMDR_0 32 H'FFC14 DMAC_0 16 2I φ/2Iφ DMA address control register_0 DACR_0 32 H'FFC18 DMAC_0 16 2I φ/2Iφ DMA source address register_1 DSAR_1 32 H'FFC20 DMAC_1 16 2I φ/2Iφ DMA destination address register_1 DDAR_1 32 H'FFC24 DMAC_1 16 2I φ/2Iφ DMA offset register_1 DOFR_1 32 H'FFC28 DMAC_1 16 2I φ/2Iφ DMA transfer count register_1 DTCR_1 32 H'FFC2C DMAC_1 16 2I φ/2Iφ DMA block size register_1 DBSR_1 32 H'FFC30 DMAC_1 16 2I φ/2Iφ DMA mode control register_1 DMDR_1 32 H'FFC34 DMAC_1 16 2I φ/2Iφ DMA address control register_1 DACR_1 32 H'FFC38 DMAC_1 16 2I φ/2Iφ DMA source address register_2 DSAR_2 32 H'FFC40 DMAC_2 16 2I φ/2Iφ DMA destination address register_2 DDAR_2 32 H'FFC44 DMAC_2 16 2I φ/2Iφ |
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