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H8SX/1663 Datasheet(PDF) 1101 Page - Renesas Technology Corp

Part # H8SX/1663
Description  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663 Datasheet(HTML) 1101 Page - Renesas Technology Corp

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Section 25 Electrical Characteristics
Rev.1.00 Jun. 07, 2006 Page 1049 of 1102
REJ09B0294-0100
Table 25.6
Bus Timing (2)
Conditions: V
CC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC,
V
SS = PLLVSS = DrVSS = AVSS = 0 V, Bφ = 8 MHz to 50 MHz,
T
a = –20°C to +75°C (regular specifications),
T
a = –40°C to +85°C (wide-range specifications)
Item
Symbol
Min.
Max.
Unit
Test
Conditions
WR delay time 1
t
WRD1
15
ns
WR delay time 2
t
WRD2
15
ns
Figures 25.8 to
25.34
WR pulse width 1
t
WSW1
1.0
× t
cyc – 13
ns
WR pulse width 2
t
WSW2
1.5
× t
cyc – 13
ns
Write data delay time
t
WDD
20
ns
Write data setup time 1
t
WDS1
0.5
× t
cyc – 13
ns
Write data setup time 2
t
WDS2
1.0
× t
cyc – 13
ns
Write data setup time 3
t
WDS3
1.5
× t
cyc – 13
ns
Write data hold time 1
t
WDH1
0.5
× t
cyc – 8
ns
Write data hold time 3
t
WDH3
1.5
× t
cyc – 8
ns
Byte control delay time
t
UBD
15
ns
Figures 25.13,
25.14
Byte control pulse width 1
t
UBW1
1.0
× t
cyc – 15
ns
Figure 25.13
Byte control pulse width 2
t
UBW2
2.0
× t
cyc – 15
ns
Figure 25.14
Multiplexed address delay time 1
t
MAD1
18
ns
Multiplexed address hold time
t
MAH
1.0
× t
cyc – 15
ns
Figures 25.17,
25.18
Multiplexed address setup time 1
t
MAS1
0.5
× t
cyc – 15
ns
Multiplexed address setup time 2
t
MAS2
1.5
× t
cyc – 15
ns
Address hold delay time
t
AHD
15
ns
Address hold pulse width 1
t
AHW1
1.0
× t
cyc – 15
ns
Address hold pulse width 2
t
AHW2
2.0
× t
cyc – 15
ns
WAIT setup time
t
WTS
15
ns
WAIT hold time
t
WTH
5.0
ns
Figures 25.10,
25.18
BREQ setup time
t
BREQS
20
ns
Figure 25.33
BACK delay time
t
BACD
15
ns
Bus floating time
t
BZD
30
ns
BREQO delay time
t
BRQOD
15
ns
Figure 25.34
BS delay time
t
BSD
1.0
15
ns
RD/
WR delay time
t
RWD
15
ns
Figures 25.8,
25.9, 25.11 to
25.14



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